Latch module and frequency divider
View Patent ↗A latch module comprising a sense pair of transistor elements coupled together for sensing a differential input signal at input terminals, a level-shift module for producing a differential output signal at output terminals, and a regenerative pair of transistor elements coupled together and with the input pair for holding the output signal through the level-shift module. The latch module also includes a pair of gate transistor elements connected in series respectively with the sense pair of transistor elements and with the regenerative pair of transistor elements and responsive to an alternating differential gate signal to activate alternately the sense pair during sense periods and the regenerative pair during store periods. A current injector provides asymmetric operation by injecting current between at least one of the gate transistors and the corresponding sense or regenerative pair of transistor elements so that the sense periods are of different duration from the store periods.
1. A latch module comprising:
a sense pair of transistor elements coupled together for sensing a differential input signal at input terminals;
a level-shift module for producing a differential output signal at output terminals;
a regenerative pair of transistor elements coupled together and with said sense pair for holding said output signal through said level-shift module;
a pair of gate transistor elements connected in series respectively with said sense pair of transistor elements and with said regenerative pair of transistor elements and responsive to an alternating differential gate signal to activate alternately said sense pair during sense periods and said regenerative pair during store periods; and
a current injector for injecting current between at least one of said gate transistors and the corresponding sense or regenerative pair of transistor elements so that said sense periods are of different duration from said store periods;
wherein said current injector is responsive to a tuning signal to control the relative durations of said sense periods and said store periods.
2. A latch module as claimed in claim 1 , wherein said current injector is arranged to inject said current between at least one of said gate transistors and the corresponding sense or regenerative pair of transistor elements so that said sense periods are of greater duration than said store periods.
3. A latch module as claimed in claim 2 , wherein said current injector is connected for injecting current to said sense pair of transistor elements in parallel with the corresponding one of said gate transistor elements.
4. A frequency divider comprising first and second latch modules, the first latch module as claimed in claim 3 and the second latch module as claimed in claim 3 , said output terminals of said first latch module being connected to supply said output signal of said first latch module to said input terminals of said second latch module, said output terminals of said second latch module being connected to supply said output signal of said second latch module inverted to said input terminals of said first latch module, and said second latch module being responsive to said gate signal inverted relative to the gate signal to which said first latch module is responsive.
5. A frequency divider comprising first and second latch modules, the first latch module as claimed in claim 2 and the second latch module as claimed in claim 2 , said output terminals of said first latch module being connected to supply said output signal of said first latch module to said input terminals of said second latch module, said output terminals of said second latch module being connected to supply said output signal of said second latch module inverted to said input terminals of said first latch module, and said second latch module being responsive to said gate signal inverted relative to the gate signal to which said first latch module is responsive.
6. A frequency divider comprising first and second latch modules, the first latch module as claimed in claim 1 and the second latch module as claimed in claim 1 , said output terminals of said first latch module being connected to supply said output signal of said first latch module to said input terminals of said second latch module, said output terminals of said second latch module being connected to supply said output signal of said second latch module inverted to said input terminals of said first latch module and said second latch module being responsive to said gate signal inverted relative to the gate signal to which said first latch module is responsive.