PLL start-up circuit
View Patent ↗A start-up circuit for a PLL includes a phase-frequency detector (PFD), one or more logic gates, a flip-flop and a false detection circuit. The false detection circuit includes a set of series connected flip-flops. The PFD receives a reference signal and a feedback signal. The PFD compares the frequency of a reference signal with that of a feedback signal. If the frequency of the reference signal is greater than the frequency of the feedback signal then a start-up signal is generated and transmitted to the PLL. The PLL increases the frequency of the feedback signal until it is greater than the frequency of the reference signal. The generation of the start-up signal is halted when the frequency of the feedback signal is greater than the frequency of the reference signal.
1. A start-up circuit for a Phase locked loop (PLL), comprising;
a phase-frequency detector (PFD) for comparing the frequency of a reference signal with the frequency of a feedback signal to generate first and second comparison signals, wherein the feedback signal is an output signal generated by the PLL;
one or more AND gates, connected to the PFD, for generating first and second intermediate signals using the first and second comparison signals;
a first flip-flop, connected to the one or more AND gates, for transmitting the first intermediate signal to the output terminal of the first flip-flop based on the second intermediate signal, wherein the first intermediate signal is received at the data input terminal of the first flip-flop and the second intermediate signal is received at the clock input terminal of the first flip-flop;
a set of second flip-flops, connected to the first flip-flop, for transmitting the first intermediate signal based on the reference signal, wherein the set of second flip-flops receives the first intermediate signal from the output terminal of the first flip-flop at the data input terminal and the reference signal at the clock input terminal; and
an OR gate, connected to the first flip-flop and the set of second flip-flops, for generating a start-up signal based on the first intermediate signal received from the first flip-flop and from the set of second flip-flops.
2. The start-up circuit of claim 1 , wherein the first and second comparison signals are pulse signals.
3. The start-up circuit of claim 2 , wherein the width of the pulses of the first comparison signal are wider than the width of the pulses of the second comparison signal when the frequency of the reference signal is greater than the frequency of the feedback signal.
4. The start-up circuit of claim 2 , wherein a positive edge of the second comparison signal is received at the clock input of the first flip-flop subsequent to the receipt of a positive edge of the first comparison signal at the data input of the first flip-flop when the frequency of the reference signal is greater than the frequency of the feedback signal.
5. The start-up circuit of claim 2 , wherein the width of the pulses of the second comparison signal are wider than the width of the pulses of the first comparison signal when the frequency of the feedback signal is greater than the frequency of the reference signal.
6. The start-up circuit of claim 5 , wherein the positive edge of the second comparison signal is received at the clock input of the first flip-flop prior to receipt of the positive edge of the first comparison signal at the data input of the first flip-flop when the frequency of the feedback signal is greater than the frequency of the reference signal.
7. A start-up circuit that generates a start-up signal for a Phase Locked Loop (PLL), wherein the PLL includes a phase-frequency detector (PFD) that compares the frequency of a reference signal with the frequency of a feedback signal and generates first and second comparison signals, and wherein the feedback signal is an output signal generated by the PLL, the start-up circuit comprising:
a first logic gate that receives the first comparison signal from the PFD and the start-up signal and generates a first intermediate signal;
a second logic gate that receives the second comparison signal from the PFD and the start-up signal and generates a second intermediate signal;
a first flip-flop connected to the first and second logic gates, wherein the first intermediate signal is provided to the data input of the first flip-flop, the second intermediate signal is provided to the clock input of the first flip-flop, and a first latched intermediate signal (S 1 ) is provided at the data output of the first flip-flop;
a set of second flip-flops including a plurality of series connected second flip-flops, wherein a first flip-flop in the series receives the first latched intermediate signal (S 1 ) at a data input, and each of the second flip-flops receives the reference signal at a clock input thereof, the second flip-flops outputting second latched intermediate signals (S 2 . . . Sn); and
a third logic gate that receives as inputs the first latched intermediate signal and each of the second latched intermediate signals (S 2 . . . Sn) and generates the start-up signal.
8. The start-up circuit of claim 7 , wherein the first flip-flop and each of the second flip-flops receives a PWD signal at a reset input thereof.
9. The start-up circuit of claim 7 , wherein the first and second logic gates comprise AND gates and the third logic gate comprises an OR gate.