Data processing with variable operand size
View Patent ↗A method of processing data comprising performing a sequence of operation instructions with variable operand size, wherein respective size codes for different source and destination operands are obtained and registered separately from performing the sequence of operation instructions, and the sequence of operation instructions is performed using operand sizes defined by the registered size codes, the operation instructions of the sequence not themselves containing size codes.
1. A method of data processing comprising:
storing a first set of register size codes for a bank of registers obtained from a register and operand size register (ROSR);
executing a single instruction for writing a second set of register size codes for the bank of registers into the ROSR;
executing a first instruction to determine a result based on a first operand and a second operand, wherein the first operand identifies a first register of the bank of registers, wherein a first size of the first register of the bank of registers for the executing the first instruction is determined from a first register size code of the second set of register size codes stored in the ROSR;
executing a second instruction to determine a result based on a third operand and a fourth operand, wherein the third operand identifies the first register of the bank of registers, wherein the first size of the first register of the bank of registers for the executing the second instruction is determined from the first register size code of the second set of register size codes stored in the ROSR;
executing a third instruction to determine a result based on a fifth operand and a sixth operand, wherein the fifth operand identifies a second register of the bank of registers, wherein a second size of the second register of the bank of registers for the executing the third instruction is determined from a second register size code of the second set of register size codes stored in the ROSR; and
executing a second single instruction for restoring the first set of register size codes for the bank of registers to the ROSR.
2. The method of claim 1 , wherein a size code is one of an 8-bit, 16-bit and 32-bit indicator.
3. The method of claim 1 , wherein a size code is obtained from the ROSR dynamically at runtime of the first, second and third instructions.
4. The method of claim 1 , wherein the first instruction is a load instruction.
5. The method of claim 4 , wherein the second instruction is a store instruction, wherein the store instruction does not contain a size code.
6. The method of claim 1 , wherein the single instruction and the first instruction is generated by a compiler.
7. The method of claim 1 , wherein the second set of size codes comprises an 8-bit indicator for the first register based upon the first, second and third instructions including a plurality of character operations.
8. The method of claim 1 , wherein the second set of size codes comprises a 16-bit indicator for the first register based upon the first, second and third instructions including a plurality of arithmetic processing operations.
9. The method of claim 1 , wherein the first, second and third instructions are included in a subroutine.
10. The method of claim 1 , wherein no op code of the first, second and third instructions designates a size code of an operand.
11. The method of claim 1 , wherein the the size code for the second operand is the first size code, wherein the first register is a destination operand of the first instruction.
12. A data processor comprising:
a bank of registers to store values of operands;
a register and operand size (ROSR) register to store register size codes for the bank of registers; and
a processor configured to:
store a first set of register size codes for the hank of registers obtained from the ROSR;
execute a single instruction to write a second set of codes the bank of registers into the ROSR;
execute a first instruction to determine a result based on a first operand and a second operand, wherein the first operand identifies a first register of the bank of resisters wherein a first size of the first register of the bank of registers for the execution of the first instruction is determined from a first register size code of the second set of register size codes stored in the ROSR;
execute a second instruction to determine a result based on a third operand and a fourth operand, wherein the third operand identifies the first register of the bank of registers, wherein the first size of the first register of the bank of registers for the execution of the second instruction is determined from the first register size code of the second set of register size codes stored in the ROSR;
execute a third instruction to determine a result based on a fifth operand and a sixth operand, wherein the fifth operand identifies a second register of the bank of registers, wherein a second size of the second register of the bank of registers for the execution of the third instruction is determined from a second register size code of the second set of register size codes stored in the ROSR; and
execute a second single instruction for restoring the first set of register size codes for the bank of registers to the ROSR.
13. The data processor of claim 12 , wherein the ROSR receives values of a plurality of size codes from a single operation instruction.
14. The data processor of claim 12 , further comprising a multiplexer in communication with the ROSR to provide size code information to the processor.
15. A system comprising the data processor of claim 12 , wherein the processor is to receive instructions from a compiler, wherein the instructions , when executed, determine the second set of size codes.
16. The data processor of claim 12 , wherein the processor is further configured to execute a third single instruction to write a third set of size codes into the ROSR based upon a task context with character processing; and to execute a fourth single instruction to write a fourth set of size codes into the ROSR based upon a task context with 32-bit operands, wherein the third and fourth sets include a size code for each register of the bank of registers.
17. The data processor of claim 12 , wherein the processor stores the first set of size codes and executes the single instruction before entering a subroutine called by a fifth instruction of a task context, and executes the second single instruction before returning to the task context from the subroutine and based upon returning from the subroutine, wherein the second set includes a size code for each register of the bank of registers.