Integrated circuit device with reduced leakage and method therefor
View Patent ↗A method includes preferentially placing fill regions adjacent to transistors of a particular conductivity type, such as p-channel transistors, for a plurality of standard cell instances of a device design. The method also includes evaluating all transistors of the first conductivity type prior to evaluating any transistors of a second conductivity type. The second conductivity type is opposite the first conductivity type. For each transistor being evaluated, it is determined whether a criterion is me. A fill region is placed within a field isolation region adjacent to the transistor if the criterion is met.
1. A method implemented at a computer aided design tool comprising:
preferentially placing fill regions adjacent to transistors of a first conductivity type for a plurality of standard cell instances of a device design to reduce leakage of the plurality of standard cell instances, wherein preferentially placing fill regions further comprises:
evaluating, using a computer, all transistors of the first conductivity type for the plurality of standard cell instances prior to evaluating any transistors of a second conductivity type for the plurality of standard cell instances, the second conductivity type opposite the first conductivity type; and
for each transistor being evaluated, determining if a criterion comprising a design rule that governs surface planarity is met, and placing the fill region within a field isolation region and adjacent to the transistor being evaluated in response to the criterion being met.
2. The method of claim 1 , wherein the transistors of the first conductivity type comprise p-channel transistors.
3. The method of claim 1 , wherein preferentially placing fill regions comprises identifying an available location within a field isolation region.
4. The method of claim 1 , wherein preferentially placing the fill region comprises placing the fill region a distance from an active region of the adjacent transistor that is equal to a value corresponding to a minimum permissible width of a shallow trench isolation feature.
5. The method of claim 1 , wherein determining if a transistor meets the criterion further comprises determining whether a standard cell that includes the transistor satisfies a timing criterion.
6. The method of claim 5 , wherein determining if the standard cell that includes the transistor satisfies the timing criterion comprises determining that each logic path of the device design that includes the standard cell operates with a timing margin greater than a predefined amount.
7. The method of claim 1 , wherein the plurality of standard cell instances includes more than 1000 standard cell instances.
8. The method of claim 1 , wherein preferentially placing fill regions comprises placing fill regions after placing substantially all standard cell instances of a device design, and wherein the placement locations of the substantially all standard cell instances are not modified by placing fill regions.
9. The method of claim 1 , wherein preferentially placing the fill regions further comprises preferentially placing a fill region adjacent to a first transistor of the first conductivity type before placing a fill region adjacent to a second transistor of the first conductivity type based on determining that the first transistor has higher leakage than does the second transistor.
10. The method of claim 9 , further comprising placing fill regions adjacent to transistors of the second conductivity type only after exhausting opportunities to place fill regions adjacent to transistors of the first conductivity type, and only when additional fill regions are required to be placed.
11. An integrated circuit data processing device comprising:
a plurality of standard cell instances, each standard cell instance including a first p-channel transistor and a first n-channel transistor; and
a plurality of fill regions defined within field isolation regions, wherein a majority of the fill regions is in closer physical proximity to p-channel transistors than to n-channel transistors and located at a distance from an active diffusion region of the corresponding p-channel transistor that does not exceed four times the value of a minimum permissible width of a shallow trench isolation feature, and wherein each fill region fills an opening of the field isolation region.
12. The device of claim 11 , wherein the majority of the fill regions are to reduce leakage at the p-channel transistors.
13. The device of claim 11 , wherein the majority of fill regions are longitudinally adjacent to p-channel transistors of instances of standard cells, wherein a longitudinal direction corresponds to a direction of current flow between a drain and a source of respective p-channel transistors.
14. The device of claim 11 , wherein the average density of the fill regions at the integrated circuit data processing device is greater at locations longitudinally adjacent to the p-channel transistors than the average density of the fill regions at locations longitudinally adjacent to the n-channel transistors, wherein a longitudinal direction corresponds to a direction of current flow between a drain and a source of respective p-channel transistors.
15. The device of claim 11 , wherein each of the field isolation regions is located contiguous to a selected standard cell of the plurality of standard cells.
16. A non-transitory computer readable medium embodying a software program, the software program comprising executable instructions configured to manipulate at least one processor to:
identify transistors of a first conductivity type at instance of standard cells of a device design, the standard cells including transistors of a first conductivity type and transistors of a second conductivity type that is opposite the first conductivity type; and
place fill regions adjacent to transistors of the first conductivity type preferentially, as opposed to placing fill regions adjacent to transistors of the second conductivity type, at locations that reduce leakage of the transistors of the first conductivity type, wherein preferentially placing fill regions further comprises placing fill regions adjacent to transistors of the second conductivity type only after exhausting opportunities to place fill regions adjacent to transistors of the first conductivity type, and only when additional fill regions are required to be placed based on a criterion comprising a design rule that governs surface planarity.
17. The computer readable medium of claim 16 , wherein to place fill regions preferentially is further to place fill regions adjacent to transistors having greater leakage before placing fill regions adjacent to transistor having relatively less leakage.
18. The computer readable medium of claim 16 , wherein to place fill regions preferentially is further to place fill regions adjacent to transistors based on determining that the transistors are associated with logic paths having a predefined amount of timing margin.