Selective cache access control apparatus and method thereof
View Patent ↗A data processor is disclosed that definitively determines an effective address being calculated and decoded will be associated with an address range that includes a memory local to a data processor unit, and will disable a cache access based upon a comparison between a portion of a base address and a corresponding portion of an effective address input operand. Access to the local memory can be accomplished through a first port of the local memory when it is definitively determined that the effective address will be associated with an address range. Access to the local memory cannot be accomplished through the first port of the local memory when it is not definitively determined that the effective address will be associated with the address range.
1. A method comprising:
receiving a first value stored at a first register of a data processor unit in response to the first register being identified by a current instruction;
determining if a portion of the first value is equal to a corresponding portion of a base address of a memory local to the data processor unit; and
preventing a cache access for the current instruction at a cache local to the data processor unit in response to the portion of the first value being equal to the corresponding portion of the base address.
2. The method of claim 1 , wherein in response to the current instruction indicating a displacement value to be added to the first value to determine an effective address, preventing includes preventing the cache access based solely upon the first portion being equal to the corresponding portion of the base address.
3. The method of claim 1 , wherein in response to the current instruction indicating a second value stored at a second register that is to be added to the first value to determine an effective address, preventing includes preventing the cache access in further response to each bit of a portion of the second value being a logical one.
4. The method of claim 1 , wherein in response to the current instruction indicating a second value stored at a second register that is to be added to the first value to determine an effective address, preventing includes preventing the cache access in further response to each bit of a portion of the second value being a logical zero.
5. The method of claim 1 , wherein in response to the current instruction indicating a second value stored is to be added to the first value to determine the effective address, preventing includes preventing the cache access in further response to a portion of a second register including all logical zeros.
6. The method of claim 1 further comprising:
calculating an effective address of a memory map based upon the first value concurrently with determining if the portion of the first value is equal to the corresponding portion of the base address of the memory; and
determining if the calculated effective address is an address corresponding to a location within the local memory.
7. The method of claim 6 further comprising:
accessing the local memory if the calculated local memory address is determined to be an address corresponding to a location within the local memory.
8. The method of claim 6 wherein a cache lookup remains enabled in response to the portion of the first value not being equal to the corresponding portion of the base register.
9. The method of claim 8 further comprising:
calculating a memory address for a cache access based upon the portion of the first value concurrently with a memory address for a local memory access; and
initiating a cache access based upon the memory address.
10. The method of claim 9 further comprising:
cancelling the cache access based upon the calculated local memory address.
11. The method of claim 1 wherein determining if the portion of the first value is equal to the corresponding portion of the base address is determined by a first portion of the data processor unit, and further comprising:
calculating, based upon the first value, an address of the local memory concurrently with determining, without using the first portion of the data processor unit, if the portion of the first value is equal to the corresponding portion of the base address.
12. A method comprising:
disabling a cache access to a cache of a data processor unit responsive to determining an effective address of an instruction operand is within a predetermined range of an address map, the predetermined range being a continuous address range including an entire address range of a local memory of the data processor unit and a reserved address range from where data cannot be accessed.
13. The method of claim 12 , wherein all of the predetermined range that does not include the local memory is at an address space above an address space of the local memory in the address map.
14. The method of claim 13 , wherein a first portion of the predetermined range that does not include the local memory is at an address space above an address space of the local memory in the address map, a second portion of the predetermined range that does not include the local memory is at an address space below the address space of the local memory in the address map.
15. A device comprising:
a pipeline of a data processor unit to identify a first register based upon a current instruction;
a local memory local to the data processor unit;
a cache coupled to the data processor unit;
the first register comprising an output coupled to the pipeline;
a base address register having an input to receive a base address value indicative of a location of the local memory, and an output coupled to the pipeline; and
a comparator coupled to the data processor unit comprising a first input coupled to receive a portion of a value stored at the first register, a second input coupled to receive a portion of a value stored at the base address register that corresponds to the portion of the value stored at the first register, and an output to provide an enable signal to prevent a current instruction from accessing the cache in response to information at the first input of the comparator being equal to information at the second input of the comparator.
16. The device of claim 15 , wherein the pipeline determines the first register based upon the opcode of the current instruction.
17. The device of claim 15 , wherein the pipeline determines the first register based upon an operand of the current instruction.
18. The device of claim 15 further comprising:
a decode module of the data processor unit coupled in parallel with the comparator, and comprising an input coupled to receive the value stored at the first register to determine an effective address of an instruction operand based upon the value stored at the first register.
19. The device of claim 18 , wherein the memory decoder further generates an error indicator that indicates the effective address of the instruction operand is invalid when information at the first input of the comparator is equal to information at the second input of the comparator.
20. The device of claim 18 , wherein the comparator is a first comparator of a plurality of comparators further comprising a second comparator comprising a first input coupled to receive a most-significant bit portion of a value stored at the second register, and providing the enable signal to prevent the current instruction from accessing the cache is further in response to determining that each bit of the most-significant bit portion is a logical one or that each bit of the most-significant bit portion is a logical zero.