IP Library Patent Application 13210393
Patent Application
App. No. 13/210,393

SEMICONDUCTOR DEVICE WITH NESTED ROWS OF CONTACTS

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Patent No.
US None
App. No.
13/210,393
Abstract

A molded surface mount semiconductor device has electrical contact elements disposed in a set of pairs of zigzag rows extending adjacent and generally parallel to opposite edges of an active face of a semiconductor die. Each of the pairs of rows includes an inner zigzag row of electrical contact elements nested inside an outer zigzag row of electrical contact elements. The electrical contact elements of the inner and outer zigzag rows are partially inter-digitated. A lead frame used in making the device also has a die pad located inside the set of pairs of zigzag rows, and an outer frame element located outside the set of pairs of zigzag rows, and which support the electrical contact elements of the inner and outer zigzag rows respectively.

Claims (27)

1 . A semiconductor device, comprising:

a semiconductor die;

electrical contact elements individually connected with said semiconductor die; and

an electrically insulating molding material that encapsulates said semiconductor die and said electrical contact elements so that the device presents a top face, a bottom active face in which said electrical contact elements are exposed, and transversely extending edges;

wherein said electrical contact elements are disposed in a set of pairs of zigzag rows extending at or adjacent and generally parallel to opposite edges of said active face, each of said pairs comprising an inner zigzag row of electrical contact elements nested inside an outer zigzag row of electrical contact elements, said electrical contact elements of said inner zigzag row and said outer zigzag row being partially inter-digitated.

2 . The semiconductor device of claim 1 , wherein said semiconductor die is mounted on a die pad disposed between said set of pairs of zigzag rows of electrical contact elements.

3 . The semiconductor device of claim 2 , wherein said molding material leaves said die pad exposed in said active face of the semiconductor device.

4 . The semiconductor device of claim 1 , wherein said electrical contact elements are disposed in two orthogonal sets of said pairs of zigzag rows, said semiconductor device forming a quad package.

5 . The semiconductor device of claim 1 , wherein said set of pairs of zigzag rows of electrical contact elements has four corner areas, and wherein each corner area includes electrical contact elements only of said outer zigzag row.

6 . A lead frame array for semiconductor devices that each present respectively a top face, a bottom active face, and transversely extending edges, each lead frame of said array comprising:

electrical contact elements disposed in a set of pairs of zigzag rows extending at or adjacent and generally parallel to opposite edges of said active face, each pair comprising an inner zigzag row of electrical contact elements nested inside an outer zigzag row of electrical contact elements, said electrical contact elements of said inner zigzag row and said outer zigzag row being partially inter-digitated; and

an inner frame element disposed inside said set of pairs of zigzag rows, and an outer frame element disposed outside said set of pairs of zigzag rows, said inner and outer frame elements connecting with and supporting said electrical contact elements of said inner and outer zigzag rows respectively, and said outer frame element of adjacent lead frames of said array being common to said adjacent lead frames.

7 . The lead frame array of claim 6 , wherein said inner frame element comprises a die pad disposed between said set of pairs of zigzag rows of electrical contact elements for mounting said semiconductor die.

8 . The lead frame array of claim 6 , wherein said electrical contact elements are disposed in two orthogonal sets of said pairs of zigzag rows, whereby to form a quad package for said semiconductor device.

9 . The lead frame array of claim 6 , wherein each lead frame has four corner areas, and wherein each corner area includes electrical contact elements only of said outer zigzag row.

10 . A method of making a semiconductor device, comprising:

providing a semiconductor die;

providing electrical contact elements;

connecting said electrical contact elements electrically with said semiconductor die; and

encapsulating with a molding material said semiconductor die and said electrical contact elements so that the device presents a top face, a bottom active face in which said electrical contact elements are exposed, and transversely extending edges;

wherein said electrical contact elements are disposed in a set of pairs of zigzag rows extending at or adjacent and generally parallel to opposite edges of said active face, each of said pairs comprising an inner zigzag row of electrical contact elements nested inside an outer zigzag row of electrical contact elements, said electrical contact elements of said inner zigzag row and said outer zigzag row being partially inter-digitated.

11 . The method of making a semiconductor device of claim 10 , further comprising:

providing a lead frame comprising said electrical contact elements, an inner frame element disposed inside said set of pairs of zigzag rows, and an outer frame element disposed outside said set of pairs of zigzag rows, said inner and outer frame elements connecting with and supporting said electrical contact elements of said inner and outer zigzag rows respectively; and

separating said electrical contact elements of said inner and outer zigzag rows from said inner and outer frame elements.

12 . The method of making a semiconductor device of claim 11 , wherein said lead frame is provided as part of an array of lead frames comprising respective sets of pairs of said inner and outer zigzag rows of electrical contact elements, and respective inner frame elements disposed inside said set of pairs of zigzag rows, and outer frame elements disposed outside said set of pairs of zigzag rows, said outer frame elements being common to adjacent lead frames of said array; and separating said electrical contact elements of said inner and outer zigzag rows from said inner and outer frame elements includes singulating said plurality of semiconductor devices.

13 . The method of making a semiconductor device of claim 12 , wherein separating said electrical contact elements of said inner zigzag rows from said inner frame elements includes cutting connections between said inner frame elements of said lead frame and said electrical contact elements of said inner zigzag rows after applying said molding material.

14 . The method of making a semiconductor device of claim 10 , wherein said electrical contact elements are disposed in two orthogonal sets of said pairs of zigzag rows, said semiconductor device forming a quad package.

Assignments (23)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0334 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0285 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0387 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027621/0928 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0075 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0477 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 16, 2011
From: LIU, QIANG; HE, QINGCHUN; TIAN, ZHAOJUN
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 026753/0305 →