Recovery method for poor yield at integrated circuit die panelization
View Patent ↗A method for making a packaged integrated circuit is provided. The method includes making a first panel of encapsulated die. In some embodiments, if a threshold number of die are not positioned in proper positions in the first panel, the die are separated from the first panel. The separated die are subsequently encapsulated in other panels of encapsulated die. Conductive interconnects can be formed over the other panels. The other panels are then separated into integrated circuit packages.
1. A method of packaging an integrated circuit die, the method comprising:
forming a first panel comprising a first plurality of integrated circuit die, wherein the first plurality of integrated circuit die are encapsulated in the first panel;
separating the first plurality of integrated circuit die from the first panel if a threshold number of the first plurality of integrated circuit die are not properly placed within the first panel, wherein
a determination of whether the threshold number of the first plurality of integrated circuit die are not properly placed is performed prior to formation or provision of an electrically conductive coupling to any of the first plurality of integrated circuit die, and
said separating is performed prior to the formation or provision of an electrically conductive coupling to any of the first plurality of integrated circuit die;
forming a second panel after said separating, the second panel comprising a second plurality of integrated circuit die, wherein
the second plurality of integrated circuit die are encapsulated in the second panel, and
the second plurality of integrated circuit die comprises at least one integrated circuit die of the first plurality of integrated circuit die separated from the first panel; and
forming a plurality of electrically conductive interconnects over the second panel, wherein the plurality of electrically conductive interconnects are coupled to conductive structures of the second plurality of integrated circuit die of the second panel.
2. The method of claim 1 further comprising:
encapsulating the first plurality of integrated circuit die in the first panel with an active surface of each integrated circuit die of the first plurality of integrated circuit die being exposed at a major surface of the first panel.
3. The method of claim 1 further comprising:
separating the second panel into a plurality of integrated circuit packages, wherein each integrated circuit package of the plurality of integrated circuit packages comprises at least one integrated circuit die of the second plurality of integrated circuit die and at least one interconnect of the plurality of electrically conductive interconnects.
4. The method of claim 1 further comprising:
forming a dielectric layer over a major surface of the second panel; and
forming a plurality of holes in the dielectric layer to expose conductive structures of the second plurality of integrated circuit die, wherein
one or more of the plurality of electrically conductive interconnects are formed on the dielectric layer.
5. The method of claim 1 , wherein
each of the first plurality of integrated circuit die comprise at least one fiducial on a surface of the integration circuit die, and
using a location of the at least one fiducial to determine whether each of the first plurality of integrated circuit die is properly placed.
6. The method of claim 1 wherein said separating the first plurality of integrated circuit die from the first panel comprises sawing the first panel.
7. The method of claim 1 comprising:
performing said separating the first plurality of integrated circuit die from the first panel to minimize an amount of encapsulant of the first panel remaining on the first plurality of integrated circuit die.
8. The method of claim 1 wherein said forming the second panel comprises forming the second panel where the at least one integrated circuit die of the first plurality of integrated circuit die includes a portion of the encapsulant of the first panel.
9. The method of claim 1 further comprising:
removing a remaining portion of an encapsulant of the first panel from the at least one integrated circuit die of the first plurality of integrated circuit die, after said separating and prior to said forming the second panel.
10. The method of claim 1 further comprising:
forming the first panel to further comprise a first encapsulated ground plane; and
forming the second panel to further comprise a second encapsulated ground plane, wherein
said separating comprises cutting the first encapsulated ground plane.
11. The method of claim 1 further comprising:
determining that the threshold number of the first plurality of integrated circuit die are not properly placed within the first panel; and
reducing the thickness of an encapsulant of the first panel, after said determining and prior to said separating.
12. The method of claim 1 wherein said separating the first plurality of integrated circuit die comprises using a laser to cut the panel.
13. The method of claim 12 further comprising:
determining a laser cutting path of the laser that minimizes an amount of encapsulant of the first panel remaining on the first plurality of integrated circuit die.
14. A method of packaging an integrated circuit die, the method comprising:
forming a first panel comprising a first plurality of integrated circuit die, wherein the first plurality of integrated circuit die are encapsulated in the first panel in an encapsulant;
separating the first plurality of integrated circuit die from the first panel, wherein
said separating is performed to minimize an amount of the encapsulant remaining on the first plurality of integrated circuit die, and
said separating is performed prior to formation or provision of an electrically conductive coupling to any of the first plurality of integrated circuit die;
forming, after said separating, a second panel comprising a second plurality of integrated circuit die, wherein
the second plurality of integrated circuit die are encapsulated in the second panel, and
the second plurality of integrated circuit die comprises at least one of the first plurality of integrated circuit die separated from the first panel; and
forming a plurality of electrically conductive interconnects over the second panel, wherein the plurality of electrically conductive interconnects are coupled to conductive structures of the second plurality of integrated circuit die of the second panel.
15. The method of claim 14 wherein no electrically conductive interconnects are formed over the first panel.