Integrated circuit having critical path voltage scaling and method therefor
View Patent ↗An integrated circuit comprises logic circuitry having a plurality of signal paths. A signal path of the plurality of signal paths has a propagation delay greater than a propagation delay of any other signal path of the plurality of signal paths. The signal path includes a plurality of components. The plurality of components is provided with a higher power supply voltage than any other signal path of the plurality of signal paths.
1. An integrated circuit comprising:
logic circuitry having a plurality of signal paths, wherein a signal path of the plurality of signal paths has a propagation delay greater than a propagation delay of any other signal path of the plurality of signal paths, wherein the signal path includes a plurality of components, and wherein the plurality of components is provided with a higher power supply voltage than any other signal path of the plurality of signal paths, and wherein the signal path includes an integral flip-flop and level shifter that includes
a data input;
a data output;
a first inverter coupled to the data input and configured to receive an input data signal at a low voltage and to output the input data signal and a logical complement of the input data signal;
a plurality of latches coupled to the first inverter, wherein the plurality of latches is configured to receive the input data signal and the logical complement of the input data signal, and to perform level shifting and latching operations to shift the low voltage input data signal to the higher power supply voltage, resulting in a high voltage data signal; and
a second inverter coupled between the plurality of latches and the data output, wherein the second inverter is configured to invert the high voltage data signal produced by the plurality of latches.
2. The integrated circuit of claim 1 , wherein the plurality of components includes a plurality of logic gates.
3. The integrated circuit of claim 1 , wherein the signal path comprises:
a first flip-flop having an input terminal and an output terminal;
a level shifter having an input terminal coupled to the output terminal of the first flip-flop, and an output terminal;
a plurality of logic gates coupled to the output terminal of the level shifter and the output terminal of the first flip-flop; and
a second flip-flop having an input terminal coupled to the plurality of logic gates.
4. The integrated circuit of claim 3 , wherein the level shifter is integral with the first flip-flop.
5. The integrated circuit of claim 4 , wherein the first flip-flop includes a master latch and a slave latch, and wherein the level shifter is integral with the master latch of the first flip-flop.
6. The integrated circuit of claim 4 , wherein the first flip-flop includes a master latch and a slave latch, and wherein the level shifter is integral with the slave latch of the flip-flop.
7. An integrated circuit comprising:
logic circuitry having a plurality of signal paths, wherein a signal path of the plurality of signal paths has a propagation delay greater than a propagation delay of any other signal path of the plurality of signal paths, wherein the signal path includes a plurality of components, and wherein the plurality of components is provided with a higher power supply voltage than any other signal path of the plurality of signal paths, wherein the signal path comprises:
a first flip-flop having an input terminal and an output terminal;
a level shifter having an input terminal coupled to the output terminal of the first flip-flop, and an output terminal, wherein the level shifter is integral with the first flip-flop;
a plurality of logic gates coupled to the output terminal of the level shifter and the output terminal of the first flip-flop; and
a second flip-flop having an input terminal coupled to the plurality of logic gates, and
wherein the first flip-flop and the integral level shifter comprises:
a master latch comprising:
a first transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode, and a second current electrode;
a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to receive an input signal, and second current electrode;
a third transistor having a first current electrode coupled to the second current electrode of the second transistor, a control electrode coupled to the control electrode of the second transistor, and a second current electrode coupled to a second power supply voltage terminal;
a fourth transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode coupled to the second current electrode of the second transistor, and a second current electrode;
a fifth transistor having a first current electrode coupled to the second current electrode of the fourth transistor, a control electrode, and a second current electrode coupled to the control electrode of the first transistor; and
a sixth transistor having a first current electrode coupled to the second current electrode of the fifth transistor, a control electrode coupled to the control electrode of the fifth transistor, and a second current electrode coupled to the second power supply voltage terminal; and
a slave latch coupled to the master latch.
8. The integrated circuit of claim 7 , wherein the slave latch comprises a pair of cross-coupled inverters.
9. An integrated circuit comprising:
logic circuitry having a plurality of signal paths, wherein a signal path of the plurality of signal paths has a propagation delay greater than a propagation delay of any other signal path of the plurality of signal paths, wherein the signal path includes a plurality of components, and wherein the plurality of components is provided with a higher power supply voltage than any other signal path of the plurality of signal paths, wherein the signal path comprises:
a first flip-flop having an input terminal and an output terminal;
a level shifter having an input terminal coupled to the output terminal of the first flip-flop, and an output terminal, wherein the level shifter is integral with the first flip-flop;
a plurality of logic gates coupled to the output terminal of the level shifter and the output terminal of the first flip-flop; and
a second flip-flop having an input terminal coupled to the plurality of logic gates, and
wherein the first flip-flop and the integral level shifter comprises:
a master latch; and
a slave latch, the slave latch comprising:
a first transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode, and a second current electrode;
a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to receive an input signal, and second current electrode;
a third transistor having a first current electrode coupled to the second current electrode of the second transistor, a control electrode coupled to the control electrode of the second transistor, and a second current electrode coupled to a second power supply voltage terminal;
a fourth transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode coupled to the second current electrode of the second transistor, and a second current electrode;
a fifth transistor having a first current electrode coupled to the second current electrode of the fourth transistor, a control electrode, and a second current electrode coupled to the control electrode of the first transistor; and
a sixth transistor having a first current electrode coupled to the second current electrode of the fifth transistor, a control electrode coupled to the control electrode of the fifth transistor, and a second current electrode coupled to the second power supply voltage terminal.
10. The integrated circuit of claim 9 , wherein the master latch comprises a pair of cross-coupled inverters.
11. An integrated circuit comprising:
logic circuitry having a first plurality of circuit components, the first plurality of circuit components coupled together to form a plurality of signal paths, wherein a signal path of the plurality of signal paths is characterized as being a critical path, wherein a second plurality of circuit components of the critical path receives a different power supply voltage than the first plurality of circuit components, the second plurality of circuit components comprising
a first flip-flop with integral level shifter having an input terminal and an output terminal;
a plurality of logic gates coupled to the output terminal; and
a second flip-flop having an input terminal coupled to the plurality of logic gates, and an output terminal,
wherein the first flip-flop and the integral level shifter comprises:
a plurality of latches configured to receive an input data signal and a logical complement of the input data signal, and to perform level shifting and latching operations to shift the low voltage input data signal to the higher power supply voltage, resulting in a high voltage data signal.
12. The integrated circuit of claim 11 , wherein the second plurality of circuit components of the critical path receives a higher power supply voltage than the first plurality of circuit components.
13. The integrated circuit of claim 11 , wherein the critical path has a longer propagation delay than substantially all of the plurality of signal paths.
14. An integrated circuit comprising:
logic circuitry having a first plurality of circuit components, the first plurality of circuit components coupled together to form a plurality of signal paths, wherein a signal path of the plurality of signal paths is characterized as being a critical path, wherein a second plurality of circuit components of the critical path receives a different power supply voltage than the first plurality of circuit components, the second plurality of circuit components comprising.
a first flip-flop with integral level shifter having an input terminal and an output terminal;
a plurality of logic gates coupled to the output terminal; and
a second flip-flop having an input terminal coupled to the plurality of logic gates, and an output terminal, and
wherein the first flip-flop with integral level shifter comprises:
a master latch comprising:
a first transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode, and a second current electrode;
a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to receive an input signal, and second current electrode;
a third transistor having a first current electrode coupled to the second current electrode of the second transistor, a control electrode coupled to the control electrode of the second transistor, and a second current electrode coupled to a second power supply voltage terminal;
a fourth transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode coupled to the second current electrode of the second transistor, and a second current electrode;
a fifth transistor having a first current electrode coupled to the second current electrode of the fourth transistor, a control electrode, and a second current electrode coupled to the control electrode of the first transistor; and
a sixth transistor having a first current electrode coupled to the second current electrode of the fifth transistor, a control electrode coupled to the control electrode of the fifth transistor, and a second current electrode coupled to the second power supply voltage terminal; and
a slave latch coupled to the master latch.
15. An integrated circuit comprising:
logic circuitry having a first plurality of circuit components, the first plurality of circuit components coupled together to form a plurality of signal paths, wherein a signal path of the plurality of signal paths is characterized as being a critical path, wherein a second plurality of circuit components of the critical path receives a different power supply voltage than the first plurality of circuit components, the second plurality of circuit components comprising.
a first flip-flop with integral level shifter having an input terminal and an output terminal;
a plurality of logic gates coupled to the output terminal; and
a second flip-flop having an input terminal coupled to the plurality of logic gates, and an output terminal, and
wherein the first flip-flop with integral level shifter comprises:
a master latch; and
a slave latch, the slave latch comprising:
a first transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode, and a second current electrode;
a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to receive an input signal, and second current electrode;
a third transistor having a first current electrode coupled to the second current electrode of the second transistor, a control electrode coupled to the control electrode of the second transistor, and a second current electrode coupled to a second power supply voltage terminal;
a fourth transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode coupled to the second current electrode of the second transistor, and a second current electrode;
a fifth transistor having a first current electrode coupled to the second current electrode of the fourth transistor, a control electrode, and a second current electrode coupled to the control electrode of the first transistor; and
a sixth transistor having a first current electrode coupled to the second current electrode of the fifth transistor, a control electrode coupled to the control electrode of the fifth transistor, and a second current electrode coupled to the second power supply voltage terminal.