Method for manufacturing a non-volatile memory, non-volatile memory device, and an integrated circuit
View Patent ↗A method of manufacturing a non-volatile memory device, including providing at least one control gate layer on a substrate. A passage may be created between the at least one control gate layer and the substrate. In the passage at least one filling layer may be provided. A floating gate structure including the filling layer may be formed, as well as a control gate structure including the at least one control gate layer, the control gate structure being in a stacked configuration with the floating gate structure.
1. A method of manufacturing a non-volatile memory device, comprising:
providing at least one control gate layer on a substrate;
creating a passage between said at least one control gate layer and said substrate, said passage extending from a first opening at a drain location of the non-volatile memory device to a second opening at a source location of the non-volatile memory device;
providing in said passage at least one filling layer; and
forming a floating gate structure including said filling layer and forming a control gate structure including said at least one control gate layer, said control gate structure being in a stacked configuration with said floating gate structure.
2. A method as claimed in claim 1 , wherein said passage is created between said substrate and a dielectric layer, said dielectric layer being positioned between said substrate and said control gate layer.
3. A method as claimed in claim 2 , wherein said passage is created between said substrate and an electrically conducting layer, which electrically conducting layer is positioned between said dielectric layer and said substrate; and wherein said providing in said passage at least one filling layer comprises includes:
providing at least one dielectric layer which separates said electrically conducting layer from a channel of the non-volatile memory device.
4. A method as claimed in claim 3 , comprising providing in said passage at least one dielectric layer which separates a floating gate layer from said at least one control gate layer.
5. A method as claimed in claim 2 , comprising providing in said passage at least one dielectric layer which separates a floating gate layer from said at least one control gate layer.
6. A method as claimed in claim 2 , wherein said providing in said passage at least one filling layer comprises:
providing in said passage at least one floating gate dielectric layer; and
providing in said passage at least one floating gate layer.
7. A method as claimed in claim 2 , wherein at least one filling layer in a first region is formed of a first material and in a second region is formed of a second material different from the first material.
8. A method as claimed in claim 1 , comprising providing in said passage at least one dielectric layer which separates a floating gate layer from said at least one control gate layer.
9. A method as claimed in claim 1 , wherein said providing in said passage at least one filling layer comprises:
providing in said passage at least one floating gate dielectric layer; and
providing in said passage at least one floating gate layer.
10. A method as claimed in claim 1 , wherein at least one filling layer in a first region is formed of a first material and in a second region is formed of a second material different from the first material.
11. A method as claimed in claim 10 , wherein said first region comprises:
a first gate region of a conducting material, for forming a first floating gate and
a second gate region of a conducting material, for forming a second floating gate, and
said second region includes a dielectric region of a dielectric material which separates said first gate region from said second gate region.
12. A method as claimed in claim 11 , wherein said dielectric material is a gas or mixture of gasses, such as air.
13. A method as claimed in claim 1 , wherein:
said passage is at least defined by a control gate side wall and a channel side wall facing the control gate side wall, and
said providing in said passage at least one filling layer comprises:
providing a dielectric layer on at least one of said control gate side wall and said channel side wall.
14. A method as claimed in claim 1 , wherein said channel side wall is formed by a substrate layer.
15. A method as claimed in claim 1 , wherein said at least one control gate layer is provided on at least one intermediate layer which separates the control gate layer from a substrate.
16. A method as claimed in claim 15 , wherein said at least one intermediate layer includes at least one sacrificial layer, and wherein said creating said passage includes removing said sacrificial layer where desired.
17. A method as claimed in claim 15 , wherein said at least one intermediate layer and/or said filling layer include one of more of the group consisting of: SiGe layer, Si layer, SiGeC layer, epitaxial layer, polycrystalline layer, crystalline layer.
18. The method of claim 1 , wherein said passage is positioned such that said passage is surrounded on at least two sides by the same material.
19. A non-volatile memory device comprising:
at least one control gate layer on a substrate;
a passage between said at least one control gate layer and said substrate, said passage extending from a first opening at a drain location of the non-volatile memory device to a second opening at a source location of the non-volatile memory device, in which said passage includes at least one filling layer; and
a floating gate structure including said filling layer and a control gate structure including said at least one control gate layer, said control gate structure being in a stacked configuration with said floating gate structure.
20. An integrated circuit including a die comprising:
a memory area with at least one non-volatile memory device as claimed in claim 19 ; and
a logic area with at least one logic device.