IP Library Granted Patent US 8,624,312
Granted Patent B2
US 8,624,312 · App. 13/096,543 · Granted Jan 7, 2014

Semiconductor device structure as a capacitor

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Quick Facts
Patent No.
US 8,624,312
App. No.
13/096,543
Granted
Jan 7, 2014
Kind
B2
Abstract

A capacitor structure includes a conductive region; a first dielectric layer over the conductive region; a conductive material within the first dielectric layer, wherein the conductive material is on the conductive region and forms a first plate electrode of the capacitor structure; an insulating layer within the first dielectric layer and surrounding the conductive material; a first conductive layer within the first dielectric layer and surrounding the insulating layer, wherein the first conductive layer forms a second plate electrode of the capacitor structure; a second conductive layer laterally extending from the first conductive layer at a top surface of the first dielectric layer; a second dielectric layer over the first dielectric layer; and a third conductive layer within the second dielectric layer and on the conductive material.

Claims (19)

1. A capacitor structure, comprising: a conductive region; a first dielectric layer over the conductive region; a conductive material within the first dielectric layer, wherein the conductive material is on and contacts the conductive region and forms a first plate electrode of the capacitor structure; an insulating layer within the first dielectric layer and contacting opposing sides of the conductive material in a cross sectional view; a first conductive layer within the first dielectric layer and surrounding the insulating layer, wherein the first conductive layer forms a second plate electrode of the capacitor structure; a second conductive layer having a lateral extension of a first length from the first conductive layer at a top surface of the first dielectric layer; a second dielectric layer over the first dielectric layer; and a third conductive layer within the second dielectric layer and on and in contact with the conductive material.

2. The capacitor structure of claim 1 , further comprising a semiconductor layer, wherein the semiconductor layer comprises the conductive region and the first dielectric layer is over the semiconductor layer.

3. The capacitor structure of claim 2 , wherein the conductive region comprises a doped region.

4. The capacitor structure of claim 3 , wherein the doped region is a source/drain region of a transistor formed in and on the semiconductor layer.

5. The capacitor structure of claim 3 , wherein the doped region is a well tie region.

6. A capacitor structure comprising: a semiconductor layer comprising a conductive region, wherein the conductive region comprises a doped region wherein the doped region comprises a gate region of a transistor formed in and on the semiconductor layer; a first dielectric layer over the conductive region and the semiconductor layer; a conductive material within the first dielectric layer, wherein the conductive material is on the conductive region, contacts the conductive region, and forms a first plate electrode of the capacitor structure; an insulating layer within the first dielectric layer and surrounding the conductive material; a first conductive layer within the first dielectric layer and surrounding the insulating layer, wherein the first conductive layer forms a second plate electrode of the capacitor structure; a second conductive layer laterally extending from the first conductive layer at a top surface of the first dielectric layer; a second dielectric layer over the first dielectric layer; and a third conductive layer within the second dielectric layer and on the conductive material.

7. The capacitor structure of claim 1 , wherein the conductive region comprises a metal.

8. The capacitor structure of claim 1 , wherein the insulating layer comprises a material having a dielectric constant greater than approximately 7.5.

9. The capacitor structure of claim 1 , wherein the insulating layer comprises a plurality of insulating layers.

10. A capacitor structure comprising: a conductive region; a first dielectric layer over the conductive region; a conductive material within the first dielectric layer, wherein the conductive material is on the conductive region, contacts the conductive region, and forms a first plate electrode of the capacitor structure; an insulating layer within the first dielectric layer and surrounding the conductive material; a first conductive layer within the first dielectric layer and surrounding the insulating layer, wherein the first conductive layer forms a second plate electrode of the capacitor structure; a second conductive layer laterally extending from the first conductive layer at a top surface of the first dielectric layer; a second dielectric layer over the first dielectric layer; a third conductive layer within the second dielectric layer and on the conductive material; and a fourth conductive layer within the second dielectric layer and on the second conductive layer.

11. The capacitor structure of claim 1 , wherein each of the first conductive layer and the insulating layer does not fully extend through the first dielectric layer to the conductive region.

12. The capacitor structure of claim 1 , wherein the second conductive layer is within the top surface of the first dielectric layer.

13. The capacitor structure of claim 1 , wherein the second conductive layer has a thickness of less than approximately 50 nanometers.

14. A capacitor structure, comprising: a conductive region, wherein the conductive region is selected from a group consisting of a doped region of a semiconductor layer or a metal; a first dielectric layer over the conductive region; a conductive material within the first dielectric layer, wherein the conductive material is on the conductive region, contacts the conductive region, and forms a first plate electrode of the capacitor structure; an insulating layer within the first dielectric layer and surrounding the conductive material; a first conductive layer within the first dielectric layer and surrounding the insulating layer, wherein the first conductive layer forms a second plate electrode of the capacitor structure; a second conductive layer laterally extending from the first conductive layer at a top surface of the first dielectric layer; a second dielectric layer over the first dielectric layer; a third conductive layer within the second dielectric layer and on the conductive material; and a fourth conductive layer within the second dielectric layer and on the second conductive layer.

15. The capacitor structure of claim 14 , wherein the conductive region is a doped region of a semiconductor layer, wherein the doped region comprises one of a group consisting of a source/drain region of a transistor formed in and on the semiconductor layer, a well tie region, and a gate region of a transistor formed in and on the semiconductor layer.

16. The capacitor structure of claim 14 , wherein the insulating layer comprises a material having a dielectric constant greater than approximately 7.5.

17. The capacitor structure of claim 14 , wherein the insulating layer comprises a plurality of insulating layers.

18. The capacitor structure of claim 14 , wherein each of the first conductive layer and the insulating layer does not fully extend through the first dielectric layer to the conductive region.

19. A capacitor structure, comprising: a semiconductor layer; a doped region formed in a top surface of the semiconductor layer, wherein the doped region is selected from a group consisting of a source/drain region of a transistor formed in and on the semiconductor layer, a gate region of a transistor formed in and on the semiconductor layer, and a well tie region; a first dielectric layer over the semiconductor layer and the doped region; a conductive material within the first dielectric layer, wherein the conductive material is on the doped region, contacts the doped region, and forms a first plate electrode of the capacitor structure; an insulating layer within the first dielectric layer and surrounding the conductive material; a first conductive layer within the first dielectric layer and surrounding the insulating layer, wherein the first conductive layer forms a second plate electrode of the capacitor structure, wherein each of the first conductive layer and the insulating layer does not fully extend through the first dielectric layer to the doped region; a second conductive layer laterally extending from the first conductive layer at a top surface of the first dielectric layer; a second dielectric layer over the first dielectric layer; a third conductive layer within the second dielectric layer and on the conductive material; and a fourth conductive layer within the second dielectric layer and on the second conductive layer.

Assignments (21)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0285 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0387 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0334 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0477 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0075 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027621/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2011
From: HALL, MARK D.; SHROFF, MEHUL D.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 026199/0381 →