Method for forming a toroidal inductor in a semiconductor substrate
View Patent ↗A toroidal inductor formed in a semiconductor substrate. Through-silicon vias are used to connect metal layers formed on top and bottom surfaces of the semiconductor substrate. In one embodiment, the vias are elongated and laid out in two concentric circles, an inner circle enclosed by an outer circle. The vias of the outer concentric circle are longer than the vias of the inner circle so that spaces between vias are the same for both circles. In another embodiment, each elongated via may include a plurality of circular vias formed in a line. Metals layers on the top and bottom of the semiconductor substrate are patterned to form wedge shaped connectors between the inner and outer vias to form the spirals of the toroidal inductor. The wedge shaped connectors with elongated vias allow spacing between spirals to be constant.
1. A method for forming a toroidal inductor, the method comprising:
forming a first plurality of conductive vias in a top surface of a semiconductor layer and a second plurality of conductive vias in the top surface of the semiconductor layer, wherein the first plurality of conductive vias is formed in a first circular pattern in the semiconductor layer and the second plurality of conductive vias is formed in a second circular pattern in the semiconductor layer, wherein the second circular pattern surrounds the first circular pattern, and wherein each of the first and second plurality of conductive vias extend into the semiconductor layer from the top surface towards a bottom surface of the semiconductor layer, opposite the top surface, and wherein each of the second plurality of conductive vias has a length along the top surface of the semiconductor layer that is longer than a length of each of the first plurality of conductive vias along the top surface of the semiconductor layer;
forming a first patterned conductive layer over the top surface of the semiconductor layer and over the first and second plurality of conductive vias, wherein the first patterned conductive layer has a first plurality of conductive portions, each conductive portion of the first plurality of conductive portions being in contact with a corresponding conductive via of the first plurality of conductive vias and a corresponding conductive via of the second plurality of conductive vias;
removing a portion of the semiconductor layer from the bottom surface of the semiconductor layer to expose each of the first and second plurality of conductive vias at the bottom surface of the semiconductor layer; and
forming a second patterned conductive layer over the bottom surface of the semiconductor layer and over the first and second plurality of conductive vias at the bottom surface of the semiconductor layer, wherein the semiconductor layer and the first and second plurality of conductive vias are between the first patterned conductive layer and the second patterned conductive layer, wherein the second patterned conductive layer has a second plurality of conductive portions, each conductive portion of the second plurality of conductive portions being in contact with a corresponding conductive via of the first plurality of conductive vias and a corresponding conductive via of the second plurality of conductive vias, wherein the first patterned conductive layer, the first plurality of conductive vias, the second plurality of conductive vias, and the second patterned conductive layer form a toroidal inductor coil.
2. The method of claim 1 , wherein the forming the first plurality of conductive vias and the second plurality of conductive vias is performed such that the second circular pattern surrounds at least 90% of the first circular pattern.
3. The method of claim 2 , wherein the forming the first plurality of conductive vias and the second plurality of conductive vias is performed such that the first circular pattern is concentric to the second circular pattern.
4. The method of claim 1 , wherein the forming the first plurality of conductive vias and the second plurality of conductive vias comprises:
forming a first plurality of openings for the first plurality of conductive vias and a second plurality of openings for the second plurality of conductive vias; and
at least partially filling each of the first plurality of openings and each of the second plurality of openings with a conductive material.
5. The method of claim 4 , wherein the forming the first plurality of conductive vias and the second plurality of conductive vias further comprises:
prior to the at least partially filling, forming a liner layer in each of the first plurality of openings and each of the second plurality of openings.
6. The method of claim 1 , further comprising:
forming a dielectric layer over the top surface of the semiconductor layer, wherein each of the first plurality of conductive vias and the second plurality of conductive vias are formed such that they extend through the dielectric layer into the top surface of the semiconductor layer, and wherein the first patterned conductive layer is formed over the dielectric layer.
7. The method of claim 1 , wherein after the forming the first plurality of conductive vias and the second plurality of conductive vias and prior to the forming the first patterned conductive layer, the method further comprises:
forming a contact to a transistor formed in and on the top surface of the semiconductor layer.
8. The method of claim 7 , wherein the first patterned conductive layer is formed such that a separate conductive portion of the first patterned conductive layer is formed over and in contact with the contact to the transistor.
9. The method of claim 1 , wherein the forming the first plurality of conductive vias and the second plurality of conductive vias is performed such that a distance between immediately adjacent conductive vias of the first plurality of conductive vias and a distance between immediately adjacent conductive vias of the second plurality of conductive vias have a same value.
10. The method of claim 1 , wherein the forming the first plurality of conductive vias and the second plurality of conductive vias is performed such that immediately adjacent edges of immediately adjacent conductive portions of the first patterned conductive layer are parallel to each other.
11. The method of claim 1 , wherein each of the first plurality and the second plurality of conductive vias comprises a different conductive material than the first patterned conductive layer.
12. A method for forming a toroidal inductor, the method comprising:
forming a dielectric layer over a top surface of a semiconductor layer;
forming a first plurality of conductive vias in the dielectric layer and extending into the top surface of the semiconductor layer and a second plurality of conductive vias in the dielectric layer and extending into the top surface of the semiconductor layer, wherein the first plurality of conductive vias is formed in a first circular pattern in the semiconductor layer and the second plurality of conductive vias is formed in a second circular pattern in the semiconductor layer, wherein the first circular pattern is concentric to the second circular pattern, and wherein each of the first and second plurality of conductive vias extend into the semiconductor layer from the top surface towards a bottom surface of the semiconductor layer, opposite the top surface, and wherein each of the second plurality of conductive vias has a length along the top surface of the semiconductor layer that is longer than a length of each of the first plurality of conductive vias along the top surface of the semiconductor layer;
forming a first patterned conductive layer over the dielectric layer and over the first and second plurality of conductive vias, wherein the first patterned conductive layer has a first plurality of conductive portions, each conductive portion of the first plurality of conductive portions being in contact with one conductive via of the first plurality of conductive vias and one conductive via of the second plurality of conductive vias;
removing a portion of the semiconductor layer from the bottom surface of the semiconductor layer to expose each of the first and second plurality of conductive vias at the bottom surface of the semiconductor layer; and
forming a second patterned conductive layer over the bottom surface of the semiconductor layer and over the first and second plurality of conductive vias at the bottom surface of the semiconductor layer, wherein the semiconductor layer and the first and second plurality of conductive vias are between the first patterned conductive layer and the second patterned conductive layer, wherein the second patterned conductive layer has a second plurality of conductive portions, each conductive portion of the second plurality of conductive portions being in contact with a corresponding conductive via of the first plurality of conductive vias and a corresponding conductive via of the second plurality of conductive vias, wherein each conductive via of the first plurality of conductive vias and each conductive via of the second plurality of conductive vias is in contact with one conductive portion of the first plurality of conductive portions and one conductive portion of the second plurality of conductive portions, such that the first patterned conductive layer, the first plurality of conductive vias, the second plurality of conductive vias, and the second patterned conductive layer form a toroidal inductor coil.
13. The method of claim 12 , wherein the forming the first plurality of conductive vias and the second plurality of conductive vias comprises:
forming a first plurality of openings in the dielectric layer and the semiconductor layer for the first plurality of conductive vias and a second plurality of openings in the dielectric layer and the semiconductor layer for the second plurality of conductive vias; and
at least partially filling each of the first plurality of openings and each of the second plurality of openings with a conductive material.
14. The method of claim 13 , wherein the forming the first plurality of conductive vias and the second plurality of conductive vias further comprises:
prior to the at least partially filling, forming a liner layer in each of the first plurality of openings and each of the second plurality of openings.
15. The method of claim 12 , wherein:
prior to the forming the dielectric layer, the method further comprises forming a transistor in and on the top surface of the semiconductor layer, wherein the dielectric layer is formed over the transistor; and
after the forming the first and second plurality of conductive vias, the method further comprises forming a contact to the transistor.
16. The method of claim 15 , wherein the first patterned conductive layer is formed such that a separate conductive portion of the first patterned conductive layer is formed over and in contact with the contact to the transistor.
17. The method of claim 12 , wherein the forming the first plurality of conductive vias and the second plurality of conductive vias is performed such that a distance between immediately adjacent conductive vias of the first plurality of conductive vias and a distance between immediately adjacent conductive vias of the second plurality of conductive vias have a same value.
18. The method of claim 12 , wherein the forming the first plurality of conductive vias and the second plurality of conductive vias is performed such that immediately adjacent edges of immediately adjacent conductive portions of the first patterned conductive layer are parallel to each other.
19. A method for forming a toroidal inductor, the method comprising:
forming a first plurality of conductive vias in a top surface of a semiconductor layer and a second plurality of conductive vias in the top surface of the semiconductor layer, wherein the first plurality of conductive vias is formed in a first circular pattern in the semiconductor layer and the second plurality of conductive vias is formed in a second circular pattern in the semiconductor layer, wherein the second circular pattern surrounds the first circular pattern, and wherein each of the first and second plurality of conductive vias extend into the semiconductor layer from the top surface towards a bottom surface of the semiconductor layer, opposite the top surface,
forming a first patterned conductive layer over the top surface of the semiconductor layer and over the first and second plurality of conductive vias, wherein the first patterned conductive layer has a first plurality of conductive portions, each conductive portion of the first plurality of conductive portions being in contact with a corresponding conductive via of the first plurality of conductive vias and a corresponding conductive via of the second plurality of conductive vias, wherein immediately adjacent edges of immediately adjacent conductive portions of the first patterned conductive layer are parallel to each other;
grinding the bottom surface of the semiconductor layer to expose each of the first and second plurality of conductive vias; and
forming a second patterned conductive layer over the bottom surface of the semiconductor layer and over the first and second plurality of conductive vias at the bottom surface of the semiconductor layer, wherein the semiconductor layer and the first and second plurality of conductive vias are between the first patterned conductive layer and the second patterned conductive layer, wherein the second patterned conductive layer has a second plurality of conductive portions, each conductive portion of the second plurality of conductive portions being in contact with a corresponding conductive via of the first plurality of conductive vias and a corresponding conductive via of the second plurality of conductive vias, wherein immediately adjacent edges of immediately adjacent conductive portions of the second patterned conductive layer are parallel to each other, and wherein the first patterned conductive layer, the first plurality of conductive vias, the second plurality of conductive vias, and the second patterned conductive layer form a toroidal inductor coil.
20. The method of claim 19 , wherein the second circular pattern surrounds at least 90% of the first circular pattern.