Scan based test architecture and method
View Patent ↗An integrated circuit architecture including architecture for a scan based test, where the integrated circuit includes N scan chain sets including one or more scan chains and an input register bank. The input register bank includes an input for serially receiving an N-bit input vector synchronous with a first clock signal, and N-outputs configured to substantially simultaneously provide the N-bits of the received input vector as N separate output bits. The N separate output bits are used to provide test bits for simultaneously shifting into the respective inputs of the scan chain set synchronous with a second clock signal.
1. An integrated circuit, comprising:
a plurality of scan chain sets N including one or more scan chains;
an input register bank including an input for serially receiving an N-bit input vector synchronous with a first clock signal, and N-outputs configured to substantially simultaneously provide the N-bits of the received input vector as N separate output bits, each output bit for providing a respective test bit for shifting into an input of a respective scan chain set synchronous with a second clock signal; and
means for deriving the second clock signal from the first clock signal, wherein the second clock signal has a signal frequency F 2 =F 1 /N, where F 1 is the frequency of the first clock signal.
2. The integrated circuit of claim 1 , further including means for enabling a test operation after each scan chain N has received a complete test vector comprising plural test bits, said test operation loading each scan chain set with plural result bits;
and an output register bank including N inputs, each input for serially receiving result bits for a respective scan chain set synchronous with the second clock signal,
wherein the output register bank is configured to serially output synchronous with the first clock signal, an N-bit output vector comprising corresponding result bits for each scan chain set at an output of the integrated circuit.
3. The integrated circuit of claim 2 , further including compression logic coupled to the output register bank, the compression logic for receiving an output bit from each scan chain of a scan chain set and compressing the output bits to provide the result bits for shifting into the output register bank synchronous with the second clock signal.
4. The integrated circuit of claim 1 , further comprising additional logic for deriving from the first clock signal a load signal for enabling the output register bank to substantially simultaneously receive the separate result bits for the respective scan chains set synchronous with the second clock signal.
5. The integrated circuit of claim 1 , wherein the input register bank comprises N shift registers, each shift register receiving the first clock signal as a clock input.
6. The integrated circuit of claim 1 , further including decompression logic coupled to the input register bank, the decompression logic for receiving the N separate output bits and decompressing received N separate output bits to obtain the test bits for shifting into respective scan chains set synchronous with the second clock signal.
7. A method of loading plural test vectors v 1 , v 2 , v 3 , . . . ,v N for a scan based test into a test circuit of an integrated circuit, wherein the test circuit comprises N plural scan chain sets, the method comprising:
forming the test vectors v 1 , v 2 , v 3 , . . . ,v N , each test vector for testing a respective scan chain set and comprising plural test bits b 1 , b 2 , b 3 , . . . , b m ;
assembling corresponding test bits b i of each test vector v 1 , v 2 , v 3 , . . . ,v N into plural N-bit input vectors a i such than a i =v 1 [b i ], v 2 [b i ], v 3 [b i ], . . . , v N [b i ], where i=1 to m;
synchronous with a first clock signal, consecutively serially inputting each N-bit input vector a i into an N-bit input register bank of the integrated circuit and shifting synchronous with a second clock signal each test bit of each input vector a i substantially simultaneously into a respective scan chain set.
8. The method of loading plural test vectors of claim 7 , further comprising:
performing scan based testing of the integrated circuit using the test vectors to obtain corresponding plural result vectors r 1 , r 2 , r 3 , . . . , r N , wherein each result vector includes result bits t 1 , t 2 , t 3 , . . . , t m ;
synchronous with the first clock signal, substantially simultaneously receiving a separate corresponding result bit b r from each scan chain set, each result bit being a bit from a respective result vector r 1 , r 2 , r 3 , . . . ,r N ;
synchronous with a second clock signal, serially outputting an N-bit vector from an output of the integrated circuit, the N-bit vector including corresponding result bits b i for each result vector; and
processing plural consecutive output N-bit vectors to assemble corresponding result bits t i of each N-bit vector into the result vectors r 1 , r 2 , r 3 , . . . , r N .
9. A method of testing an integrated circuit including a test circuit, the test circuit comprising plural (N) scan chain sets, the method comprising:
serially inputting plural input vectors into an input of the integrated circuit during m input cycles;
after each input cycle, substantially simultaneously causing a test bit to be shifted into each scan chain set, each test bit being attributable to a respective bit of the input vector;
after input of m input vectors, enabling a test of the test circuit, said test causing each scan chain of a scan chain set to be loaded with a respective result vector, each result vector comprising plural result bits;
substantially simultaneously shifting each result bit out of the test circuit during m output cycles, each output cycle causing an output register of the integrated circuit to be loaded with an N-bit vector comprising plural bits, each being attributable to a respective result bit; and
after each output cycle, serially outputting an N-bit vector from an output of the integrated circuit, the N-bit vector including corresponding result bits b i for each result vector.