Apparatus and method for decoupling asynchronous clock domains
View Patent ↗A circuit and method for synchronizing signals between asynchronous clock domains within digital electronic circuits decouples asynchronous clocks. The timing of the slower clock is used to prevent read and write to counters so that write signals from the fast clock domain can be directly used in the slower clock domain when the counters are not toggling. This feature removes the need for sampling and holding the data on the fast clock, which would require consume additional power and require additional circuit area.
1. A circuit for transmitting a signal between different clock domains, the circuit comprising:
a first clock domain having a first clock with a first clock cycle, the first clock domain arranged to transmit an enable signal and a load signal;
a second clock domain having a second clock with a second clock cycle different from the first clock cycle of the first clock, the second clock domain arranged to receive the enable signal and the load signal from the first clock domain; and
a counter and a clock and timing controller disposed in the second clock domain and operating at the second clock cycle, the clock and timing controller for asserting an adjusted clock derived from the second clock to increment the counter, and the counter for loading a value upon receiving the load signal and a resulting clock combined from the enable signal and the adjusted clock from the clock and timing controller.
2. The circuit of claim 1 , further comprising a processor located in the first clock domain, wherein the clock and timing controller generates an invalidate signal that causes the processor to prevent subsequent enable and load signals to be transmitted from the first clock domain until the counter has been incremented.
3. The circuit of claim 2 , wherein the invalidate signal is asserted when the adjusted clock is generated.
4. The circuit of claim 3 , wherein the invalidate signal is asserted for two clock cycles of the second clock of the second clock domain.
5. The circuit of claim 2 , wherein the clock and timing controller, upon incrementing the counter, de-asserts the invalidate signal to the first clock domain thereby allowing the processor to transmit another enable signal and another load signal to the second clock domain.
6. The circuit of claim 2 , further comprising a synchronizer to provide a synchronized clock to synchronize the invalidate signal transmitted to the first clock domain from the second clock domain.
7. The circuit of claim 6 , wherein the circuit forms a real time clock circuit domain and the synchronizer is located external to the real time clock circuitry.
8. The circuit of claim 1 , further comprising an OR gate that receives the enable signal from the first clock domain and the adjusted clock generated from the clock and timing controller and provides the resulting clock to the counter.
9. The circuit of claim 1 , wherein the first clock cycle of the first clock domain is faster than the second clock cycle of the second clock domain.
10. The circuit of claim 1 , wherein the circuit forms part of a system on chip (SoC).
11. The circuit of claim 1 , wherein there are at least two counters in the second clock domain, and the clock and timing controller generates different adjusted clocks for each counter.
12. The circuit of claim 1 , wherein the clock of the second clock domain is an oscillator.
13. The circuit of claim 1 , wherein the clock of the second clock domain is a 32.768 kHz clock.
14. The circuit of claim 1 , further comprising a processor disposed in the first clock domain, wherein the clock of the first clock domain is a gated bus clock that toggles upon the processor sending an enable signal and a load signal to the second clock domain.
15. A method of transmitting a signal between different clock domains, the method comprising:
transmitting an enable signal and a load signal from a first clock domain having a first clock with a first clock cycle;
receiving the enable signal and the load signal at a second clock domain having a second clock with a second clock cycle different from the first clock cycle of the first clock, the second clock domain having a counter and a clock and timing controller operating at the second clock cycle;
asserting an adjusted clock derived from the second clock from the clock and timing controller to increment the counter; and
loading a value in the counter upon receiving the load signal and a resulting clock combined from the enable signal and the adjusted clock from the clock and timing controller.
16. The method of transmitting a signal of claim 15 , further comprising generating an invalidate signal from the clock and timing controller of the second clock domain preventing a subsequent enable signal and a subsequent load signal to be transmitted from the first clock domain until the counter has incremented.
17. The method of transmitting a signal of claim 16 , wherein asserting the invalidate signal when the adjusted clock is generated.
18. The method of transmitting a signal of claim 17 , wherein asserting the invalidate signal for two clock cycles of the second clock of the second clock domain.
19. The method of transmitting a signal of claim 17 , further comprising de-asserting the invalidate signal to the first clock domain upon incrementing the counter allowing another enable signal to be transmitted from the first clock domain to the second clock domain.
20. The method of transmitting a signal of claim 16 , further comprising combining the adjusted clock and the enable signal in accordance with OR logic for providing the resulting clock to the counter.