Patterning a gate stack of a non-volatile memory (NVM) with formation of a metal-oxide-semiconductor field effect transistor (MOSFET)
View Patent ↗A first dielectric layer is formed on a substrate in a transistor region and an NVM region, a first conductive layer is formed on the first dielectric layer, a second dielectric layer is formed on the first conductive layer, and a second conductive layer is formed over the second dielectric layer. A patterned etch is performed to remove at least a portion of the second conductive layer in the transistor region and to expose an extension portion of the first conductive layer. A first mask is formed over the transistor region having a first pattern, wherein the first pattern is of a gate stack of the MOSFET and an extension in the extension portion extending from the gate stack, and a second mask over the NVM region having a second pattern, wherein the second pattern is of a gate stack of the NVM cell. A patterned etch is then performed.
1. A method of making a MOSFET in a transistor region of a substrate and a non-volatile memory cell in an NVM region of the substrate, comprising:
forming a first dielectric layer on the substrate in the transistor region and the NVM region;
forming a first conductive layer on the first dielectric layer;
forming a second dielectric layer on the first conductive layer;
forming a second conductive layer over the second dielectric layer;
performing a patterned etch to remove at least a portion of the second conductive layer in the transistor region and to expose an extension portion of the first conductive layer in the transistor region;
forming a first mask over the transistor region having a first pattern, wherein the first pattern is of a gate stack of the MOSFET and an extension in the extension portion extending from the gate stack, and a second mask over the NVM region having a second pattern, wherein the second pattern is of a gate stack of the non-volatile memory cell;
performing a patterned etch through the second conductive layer, the second dielectric layer, and the first conductive layer to leave the first pattern of the gate stack of the MOSFET in the transistor region and the second pattern of the gate stack in the NVM region; and
implanting using the gate stack in the NVM region as a mask to provide source/drain regions adjacent to the gate stack in the NVM region and using a remaining portion of the second conductive layer and the first conductive layer of the gate stack in the MOSFET region to provide source/drain regions in the MOSFET region adjacent to the first conductive layer of the gate stack of the MOSFET.
2. The method of claim 1 , further comprising forming an isolation region in the substrate to define an active region, wherein the step of performing an implant is further characterized as forming the source/drain regions of the MOSFET in the active region.
3. The method of claim 2 , wherein the step of performing a patterned etch to remove at least a portion is further characterized by the portion being over the isolation region.
4. The method of claim 1 , wherein the gate stack in the NVM region comprises a control gate as a portion of the second conductive layer and a floating gate as a portion of the first conductive layer.
5. The method of claim 1 , further comprising forming sidewall spacers adjacent to the gate stacks in the NVM and MOSFET regions.
6. The method of claim 5 , wherein the step of performing the implant is further characterized by the sidewall spacers acting as a mask.
7. The method of claim 1 , further comprising removing the first dielectric layer adjacent to the gate stacks after the step of performing the implant.
8. The method of claim 1 , further comprising performing a patterned etch of the first conductive layer prior to the step of forming the second conductive layer in the NVM region.
9. The method of claim 1 , further comprising forming an interlayer dielectric over the gate stacks and the source/drain regions.
10. The method of claim 9 , further comprising forming contacts through the interlayer dielectric to the source/drain regions.
11. A method of making a MOSFET in a transistor region of a substrate and a non-volatile memory cell in an NVM region of the substrate, comprising:
forming a first dielectric layer on the substrate in the transistor region and the NVM region;
forming a first conductive layer on the first dielectric layer;
forming a second dielectric layer on the first conductive layer;
forming a second conductive layer over the second dielectric layer;
forming a first mask over the transistor region having a first pattern, wherein the first pattern is of a gate stack of the MOSFET, and a second mask over the NVM region having a second pattern, wherein the second pattern is of a gate stack of the non-volatile memory cell;
performing a patterned etch through the second conductive layer, the second dielectric layer, and the first conductive layer to leave the first pattern of the gate stack of the MOSFET in the transistor region and the second pattern of the gate stack in the NVM region;
forming sidewall spacers adjacent to the gate stack in the NVM region and to the gate stack in the MOSFET regions;
performing a patterned etch to remove at least a portion of the second conductive layer of the gate stack of the MOSFET to expose a portion of the first conductive layer of the gate stack of the MOSFET; and
implanting using the gate stack and sidewall spacers in the NVM region as a mask to provide source/drain regions adjacent to the gate stack in the NVM region and using a remaining portion of the second conductive layer, the first conductive layer of the gate stack, and the sidewall spacers in the MOSFET region to provide source/drain regions in the MOSFET region adjacent to the first conductive layer of the gate stack of the MOSFET.
12. The method of claim 11 , further comprising forming an isolation region in the substrate to define an active region, wherein the step of performing an implant is further characterized as forming the source/drain regions of the MOSFET in the active region.
13. The method of claim 12 , wherein the step of performing a patterned etch to remove at least a portion is further characterized by the portion being over the isolation region.
14. The method of claim 13 , wherein the gate stack in the NVM region comprises a control gate as a portion of the second conductive layer and a floating gate as a portion of the first conductive layer.
15. The method of claim 14 , further comprising removing the first dielectric layer adjacent to the gate stacks after the step of performing the implant.
16. A method of making a MOSFET in a transistor region of a substrate and a non-volatile memory cell in an NVM region of the substrate, comprising:
forming a first dielectric layer on the substrate in the transistor region and the NVM region;
forming a first conductive layer on the first dielectric layer;
forming a second dielectric layer on the polysilicon layer;
forming a second conductive layer over the second dielectric layer;
performing a step, including a first etch followed by a second etch, for etching the first conductive layer and the second conductive layer to result in an NVM gate stack in the NVM region and a transistor gate stack in the transistor region, wherein the transistor gate stack includes a portion of the second conductive layer and a first portion and a second portion of the first conductive layer, wherein the first portion is aligned with the portion of the second conductive layer and the second portion extends from the first portion away from being under the portion of the second conductive layer; and
implanting using the NVM gate stack as a mask to provide source/drain regions adjacent to the gate stack in the NVM region and using the transistor gate stack in the transistor region to provide source/drain regions in the transistor region adjacent to the first portion of the first conductive layer of the transistor gate stack of the MOSFET.
17. The method of claim 16 , wherein the step of forming the first conductive layer comprises forming a first polysilicon layer.
18. The method of claim 17 , wherein the step of forming the second conductive layer comprises forming a second polysilicon layer.
19. The method of claim 16 , wherein the first etch comprises selectively etching the first conductive layer and the second conductive layer and the second etch comprises selectively etching the first conductive layer to expose the second portion of the second conductive layer.
20. The method of claim 16 , wherein the first etch comprises selectively etching the second conductive layer to include exposing at least the second portion of the first conductive layer.