Method and circuit for calibrating data capture in a memory controller
View Patent ↗A memory controller comprises a multiplexer, a first-in, first-out memory (FIFO), a comparator, and a detection and adjustment circuit. The multiplexer receives a clock signal, a reference voltage, and a gating signal. The FIFO has a clock input coupled to an output of the multiplexer and a data input that receives data from a memory. The comparator has a first input coupled to an output of the FIFO, and a second input coupled to receive a calibration pattern. The calibration pattern is predetermined to match with a first portion of data from the FIFO, and is predetermined to not match with a second portion of data from the FIFO. The detection and adjustment circuit detects if a transition from the first portion to the second portion occurs within a predetermined time period. If the transition is not detected within the time period, a timing of the gating signal is adjusted.
1. A method comprising:
writing data comprising a first plurality of bits to a first memory, a first portion of the first plurality of bits being predetermined to match in a comparison with a second plurality of bits stored in a second memory, and a second portion of the first plurality of bits being predetermined to not match in a comparison with the second plurality of bits;
setting a time delay of a gating signal to a first value, the gating signal for aligning data read from the first memory to a clock signal;
serially reading the first plurality of bits from the first memory;
comparing the first plurality of bits to the second plurality of bits;
detecting if a transition from the first portion of the first plurality of bits to the second portion of the first plurality of bits occurs within a time period;
if the transition occurs within the time period, resetting the first value of the time delay of the gating signal by a second value; and
if the transition occurs outside of the time period, adjusting the delay of the gating signal to a third value and repeating the steps of serially reading, comparing, detecting, and adjusting until the transition occurs within the time period.
2. The method of claim 1 , wherein writing data comprising a first plurality of bits to a first memory further comprises writing data comprising a first plurality of bits to a double data rate synchronous dynamic random access memory.
3. The method of claim 1 , wherein writing data comprising a first plurality of bits to a first memory further comprises writing data comprising a first plurality of bits to first memory, the first memory being a dual data rate synchronous dynamic random access memory, a first portion of the first plurality of bits being predetermined to match in a comparison with a second plurality of bits stored in a second memory, the second memory being a internal register, and the second portion of the first plurality of bits being predetermined to not match in a comparison with the second plurality of bits.
4. The method of claim 1 , wherein setting a time delay of the gating signal to the first value further comprises setting a time delay of the gating signal to the first value, wherein the first value is a minimum value.
5. The method of claim 1 , wherein adjusting the delay of the gating signal to a third value further comprises adjusting the delay of the gating signal to a third value by incrementing the delay of the gating signal by less than one cycle of the clock signal.
6. The method of claim 1 , wherein resetting the first value of the time delay of the gating signal by a second value further comprises resetting the first value of the time delay of the gating signal by subtracting one cycle of the clock signal from the first value.
7. The method of claim 1 , wherein serially reading the first plurality of bits from the first memory further comprises writing the serially read first plurality of bits to a first-in, first-out memory (FIFO).
8. The method of claim 7 , wherein comparing the first plurality of bits to the second plurality of bits further comprises reading the first plurality of bits from the FIFO and to an input of a comparator for performing the comparing.
9. The method of claim 1 , further comprising reading from the first memory using the gating signal having the time delay reset by the second value, wherein the reading is subsequent to the step of resetting the first value of the gating signal.
10. In a data processing system having a memory controller for controlling access to a memory, a method for calibrating a gating signal with data read from the memory, the gating signal for aligning the data to a clock signal, the method comprising:
entering a gating signal calibration mode;
writing a first calibration data pattern to the memory, the first calibration data pattern having a first portion and a second portion;
writing a second calibration data pattern to a register in the memory controller, the second calibration data pattern being equal to the first portion of the first calibration data pattern, and the second calibration pattern not being equal to the second portion of the first calibration data pattern;
setting a time delay of the gating signal to a first value;
reading the first calibration data pattern from the memory to the memory controller;
comparing the first calibration data pattern to the second calibration data pattern bit-by-bit in response to the gating signal;
detecting if a transition from the first portion of the first calibration data pattern to the second portion of the first calibration data pattern occurs within a time period; and
if the transition does not occur within the time period, adjusting the time delay of the gating signal by a second value.
11. The method of claim 10 , further comprising:
re-reading the first calibration data pattern from the memory to the memory controller,
comparing the first calibration data pattern to the second calibration data pattern bit-by-bit in response to the adjusted gating signal;
detecting if a transition from the first portion of the first calibration data pattern to the second portion of the first calibration data pattern occurs within the time period;
if the transition occurs within the time period, adjusting the adjusted gating signal by a third value; and
exiting the calibration mode.
12. The method of claim 11 , further comprising reading the data from the memory using the adjusted gating signal.
13. The method of claim 10 , wherein reading the first calibration data pattern from the memory to the memory controller further comprises writing the first calibration data pattern to a first-in, first-out memory (FIFO) of the memory controller.
14. The method of claim 13 , wherein comparing the first calibration data pattern to the second calibration data pattern further comprises resetting a write pointer of the FIFO to a first entry of the FIFO.
15. The method of claim 14 , wherein detecting if a transition from the first portion of the first calibration data pattern to the second portion of the first calibration data pattern further comprises determining if the transition occurs at a predetermined entry of the FIFO.
16. A memory controller comprising:
a logic circuit having a first input for receiving a clock signal, a second input coupled to a reference voltage, a control input for receiving a gating signal, and an output;
a first-in, first-out memory (FIFO) having a clock input coupled to the output of the logic circuit, a data input coupled to receive data from a memory, and an output;
a comparator having a first input coupled to a the output of the FIFO, a second input coupled to receive a calibration pattern, the calibration pattern predetermined to match with a first portion of data from the FIFO, and the calibration pattern predetermined to not match with a second portion of data from the FIFO; and
a detection and adjustment circuit for detecting if a transition from the first portion of the data to the second portion of the data occurs within a predetermined time period, and in response to detecting that the transition does not occur within the predetermined time period, causing a timing of the gating signal to be adjusted.
17. The memory controller of claim 16 , wherein the memory is characterized as being a double data rate synchronous dynamic random access memory.
18. The memory controller of claim 16 , wherein the clock signal comprises a preamble portion, a toggling portion, and a postamble portion.
19. The memory controller of claim 18 , wherein the data is loaded into the FIFO on both rising and falling edges of the toggling portion of the clock signal.
20. The memory controller of claim 16 , wherein the FIFO further comprises a read pointer, wherein the transition occurs on a predetermined read pointer location when the transition is within the predetermined time period.