IP Library Patent Application 12830424
Patent Application
App. No. 12/830,424

METHOD OF PACKAGING SEMICONDUCTOR DEVICE

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Quick Facts
Patent No.
US None
App. No.
12/830,424
Abstract

Quad Flat No-Lead packaged devices are manufactured using two singulation operations with two different saw blades of varying widths with the first singulation operation using a wider saw blade than the second singulation operation. Between singulation operations, the exposed portions of the leads are plated with a solderable metal. By performing the second singulation operation within the first cut made by the first singulation, at least half of the exposed metal of the leads remains plated. Thus, better solder joints may be formed, which allows for simpler visual inspection.

Claims (37)

1 . A method of packaging a plurality of semiconductor devices, the method comprising:

providing a lead frame strip including a plurality of individual lead frames, each lead frame having a plurality of leads, each lead having a first end and a second end, wherein the leads extend outwardly from a generally rectangular central space, the first ends being proximate to the central space and the second ends being distal from the central space, and wherein there are one or more die pads disposed in the central space, and wherein saw streets are located between adjacent lead frames of the plurality of lead frames;

attaching semiconductor dies, each die having an integrated circuit therein, on respective first ones of the one or more die pads of the individual lead frames;

electrically connecting the leads of the individual lead frames to the respective integrated circuits of the dies;

encapsulating the semiconductor dies, the electrical connections and the leads of the individual lead frames with a mold compound, wherein at least a bottom surface of the second ends of the leads is exposed;

performing a first singulation with a first saw blade having a first blade width, along the saw streets, wherein the first singulation cuts the leads of the lead frames to a first depth;

plating exposed portions of the lead frames with a solderable metal; and

performing a second singulation with a second saw blade having a second blade width, along the saw streets and within spaces made by the first singulation, wherein the second singulation separates the lead frames from each other, thereby forming individual semiconductor packages.

2 . The method of packaging a plurality of semiconductor devices of claim 1 , wherein the lead frame strip comprises copper.

3 . The method of packaging a plurality of semiconductor devices of claim 2 , wherein the solderable metal comprises one of tin, zinc, palladium and gold.

4 . The method of packaging a plurality of semiconductor devices of claim 1 , wherein the lead frame strip at the saw streets has a thickness and the first depth is about half of said thickness.

5 . The method of packaging a plurality of semiconductor devices of claim 1 , wherein the first blade width is greater than the second blade width.

6 . The method of packaging a plurality of semiconductor devices of claim 5 , wherein the first blade width is about 0.58 mm.

7 . The method of packaging a plurality of semiconductor devices of claim 6 , wherein the second blade width is about 0.50 mm.

8 . The method of packaging a plurality of semiconductor devices of claim 7 , wherein by performing first and second singulations, about half of a side wall of the leads at the saw streets remains plated with the solderable metal after the second singulation.

9 . A method of packaging a plurality of semiconductor devices, the method comprising:

providing a lead frame strip including a plurality of individual lead frames, each lead frame having a plurality of leads, each lead having a first end and a second end, wherein the leads extend outwardly from a generally rectangular central space, the first ends being proximate to the central space and the second ends being distal from the central space, and wherein there are one or more die pads disposed in the central space, and wherein saw streets are located between adjacent lead frames of the plurality of lead frames;

attaching semiconductor dies, each die having an integrated circuit therein, on respective first ones of the one or more die pads of the individual lead frames;

electrically connecting the leads of the individual lead frames to the respective integrated circuits of the dies;

encapsulating the semiconductor dies, the electrical connections and the leads of the individual lead frames with a mold compound, wherein at least a bottom surface of the second ends of the leads is exposed;

performing a first singulation with a first saw blade having a first blade width, along the saw streets, wherein the first singulation cuts the leads of the lead frames to a first depth;

plating exposed portions of the lead frames with a solderable metal; and

performing a second singulation with a second saw blade having a second blade width, along the saw streets and within spaces made by the first singulation, wherein the first blade width is greater than the second blade width, and wherein the second singulation separates the lead frames from each other, thereby forming individual semiconductor packages.

10 . The method of packaging a plurality of semiconductor devices of claim 9 , wherein the lead frame strip comprises copper.

11 . The method of packaging a plurality of semiconductor devices of claim 10 , wherein the solderable metal comprises one of tin, zinc, palladium and gold.

12 . The method of packaging a plurality of semiconductor devices of claim 9 , wherein the lead frame strip at the saw streets has a thickness and the first depth is about half of said thickness.

13 . The method of packaging a plurality of semiconductor devices of claim 9 , wherein the first blade width is about 0.58 mm.

14 . The method of packaging a plurality of semiconductor devices of claim 13 , wherein the second blade width is about 0.50 mm.

15 . The method of packaging a plurality of semiconductor devices of claim 9 , wherein by performing first and second singulations, about half of a side wall of the leads at the saw streets remains plated with the solderable metal after the second singulation.

16 . A method of packaging a plurality of semiconductor devices, the method comprising:

providing a lead frame strip including a plurality of individual lead frames, each lead frame having a plurality of leads, each lead having a first end and a second end, wherein the leads extend outwardly from a generally rectangular central space, the first ends being proximate to the central space and the second ends being distal from the central space, and wherein there are one or more die pads disposed in the central space, and wherein saw streets are located between adjacent lead frames of the plurality of lead frames;

attaching semiconductor dies, each die having an integrated circuit therein, on respective first ones of the one or more die pads of the individual lead frames;

electrically connecting the leads of the individual lead frames to the respective integrated circuits of the dies;

encapsulating the semiconductor dies, the electrical connections and the leads of the individual lead frames with a mold compound, wherein at least a bottom surface of the second ends of the leads is exposed;

performing a first singulation with a first saw blade having a first blade width, along the saw streets, wherein the first singulation cuts the leads of the lead frames to a first depth, wherein the lead frame strip at the saw streets has a thickness and the first depth is about half of said thickness;

plating exposed portions of the lead frames with a solderable metal; and

performing a second singulation with a second saw blade having a second blade width that is less than the first saw blade width, along the saw streets and within spaces made by the first singulation, and wherein the second singulation separates the lead frames from each other, thereby forming individual semiconductor packages, and wherein by performing first and second singulations, about half of a side wall of the leads at the saw streets remains plated with the solderable metal after the second singulation.

Assignments (16)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0334 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0285 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0387 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027621/0928 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0075 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0477 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 5, 2010
From: LIU, PENG; GAO, XU; HE, QINGCHUN; QI, ZHAOBIN; YE, DEHONG
To: FREESCALE SEMICONDUCTOR, INC
Reel/Frame 024635/0469 →