Granted Patent B2

US 8,630,593 · App. 13/059,085 · Granted Jan 14, 2014

Abstract

Claims (48)

1. A method for generating a frequency signal, the method comprising:

receiving, at a synthesized frequency generator, a reference signal;

generating a divided signal based upon the reference signal, the divided signal having a period equal to N times that of the reference signal;

generating a synthesized frequency signal based upon the divided signal, the synthesized frequency signal having a period equal to 1/M that of the divided signal;

determining whether a near-integer spur arises in using the synthesized frequency signal;

selecting the synthesized frequency signal in response to determining that the near-integer spur arises; and

bypassing the synthesized frequency signal in response to determining that a near-integer spur does not arise.

2. The method of claim 1 :

N is a variable integer; and

the method further comprises receiving a value for the variable integer.

3. The method of claim 1 wherein the near-integer spur comprises a frequency spur generated when an oscillation frequency is separated from a closest harmonic of a crystal reference signal by a value smaller than a passband of a loop filter of the synthesized frequency generation logic.

4. The method of claim 1 wherein the synthesized frequency generator comprises a Delay-Locked Loop (DLL).

5. The method of claim 1 wherein the reference signal is a variable frequency reference signal.

6. A semiconductor device comprising:

synthesized frequency generation logic arranged to

receive a reference signal, and

provide an output frequency signal; and

wherein,

the synthesized frequency generation logic comprises

divider logic arranged to receive the reference signal and to generate a divided signal comprising a frequency with a period equal to N times that of the reference signal,

the synthesized frequency generation logic further arranged to generate, from the divided signal, a synthesized frequency signal comprising a frequency with a period equal to 1/M that of the divided signal,

the synthesized frequency generation logic further comprises a decision logic module and a switching logic module such that the decision logic module is arranged to determine whether a near-integer spur arises in using the synthesized frequency signal and configures the switching logic module to select the synthesized frequency signal as the output frequency signal in response thereto, and

the decision logic module is further arranged to configure the switching logic module to select another output frequency as the output frequency signal and bypass the synthesized frequency generation logic in response to determining that a near-integer spur does not arise.

7. The semiconductor device of claim 6 wherein the selected output frequency is a frequency of the reference signal.

8. The semiconductor device of claim 6 wherein the divider logic comprises fixed divider logic arranged to receive the reference signal and to generate a fixed divided signal.

9. The semiconductor device of claim 6 wherein the near-integer spur comprises a frequency spur generated when an oscillation frequency is separated from a closest harmonic of a crystal reference signal by a value smaller than a passband of a loop filter of the synthesized frequency generation logic.

10. The semiconductor device of claim 6 wherein the synthesized frequency generation logic comprises a Delay-Locked Loop (DLL).

11. The semiconductor device of claim 6 wherein the semiconductor device further comprises:

radio frequency (RF) transceiver circuitry arranged to support RF communication within a Universal Mobile Telecommunications System (UMTS).

12. The semiconductor device of claim 6 wherein the reference signal is a variable frequency reference signal.

13. A wireless communication device comprising synthesized frequency generation logic arranged to receive a reference signal and to provide an output frequency signal, the synthesized frequency generation logic comprising:

a divider module;

a delay-locked loop (DLL) synthesizer module;

a switching module; and

a decision module;

wherein:

the divider module is arranged to receive the reference signal and to generate a divided signal, the divided signal having a period equal to N times that of the reference signal,

the DLL synthesizer module is arranged to receive the divided signal and to generate a synthesized frequency signal comprising a frequency with a period equal to 1/M that of the divided signal,

the decision module is arranged to determine whether a near-integer spur arises in using the synthesized frequency signal; and

the switching module is arranged to

select the synthesized frequency signal as the output frequency signal when the decision module determines that a near-integer spur arises in using the synthesized frequency signal, and

select another output frequency signal and bypass the synthesized frequency generation logic when the decision module determines that a near-integer spur has not arisen.

14. The wireless communication device of claim 13 wherein the selected output frequency signal is a frequency of the reference signal.

15. The wireless communication device of claim 13 wherein the divider module comprises fixed divider logic arranged to receive the reference signal and to generate a fixed divided signal.

16. The wireless communication device of claim 13 wherein the near-integer spur comprises a frequency spur generated when an oscillation frequency is separated from a closest harmonic of a crystal reference signal by a value smaller than a passband of a loop filter of the synthesized frequency generation logic.

17. The wireless communication device of claim 13 wherein the semiconductor device further comprises:

radio frequency (RF) transceiver circuitry arranged to support RF communication within a Universal Mobile Telecommunications System (UMTS).

18. The wireless communication device of claim 13 wherein the reference signal is a variable frequency reference signal.

Assignments (30)