IP Library Granted Patent US 8,390,369
Granted Patent B2
US 8,390,369 · App. 12/850,650 · Granted Mar 5, 2013

Electronic circuit and method for operating a module in a functional mode and in an idle mode

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Quick Facts
Patent No.
US 8,390,369
App. No.
12/850,650
Granted
Mar 5, 2013
Kind
B2
Abstract

A method and an electronic circuit, the electronic circuit includes: a module that comprises multiple flip-flops and a control signal providing circuit; a power management circuit arranged to provide to the module a supply voltage of a functional level when the module is in a functional mode, and to provide to the module a supply voltage of an idle level when the module is in an idle mode; wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the functional mode, a control signal that facilitates a state change of each of the multiple flip-flops; wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the idle mode, a control signal that prevents a state change of each of the multiple flip-flops; wherein the each of the control signal providing circuit and a plurality of flip-flops of the multiple flip-flops comprises at least one hybrid circuit that comprises a low-threshold transistor that is coupled in parallel to at least one high-threshold transistor; wherein each hybrid circuit is arranged to maintain information or a control signal when provided with the supply voltage of the idle level; and wherein high-threshold transistors of each hybrid circuit are arranged to maintain information or a control signal when provided with a supply voltage of a level that is higher than the idle level.

Claims (57)

1. An electronic circuit, comprising:

a module that comprises multiple flip-flops and a control signal providing circuit;

a power management circuit arranged to provide to the module a supply voltage of a functional level when the module is in a functional mode, and to provide to the module a supply voltage of an idle level when the module is in an idle mode;

wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the functional mode, a control signal that facilitates a state change of each of the multiple flip-flops;

wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the idle mode, a control signal that prevents a state change of each of the multiple flip-flops;

wherein each of the control signal providing circuit and a plurality of flip-flops of the multiple flip-flops comprises at least one hybrid circuit that comprises a low-threshold transistor that is coupled in parallel to at least one high-threshold transistor;

wherein each hybrid circuit is arranged to maintain information or a control signal when provided with the supply voltage of the idle level;

wherein high-threshold transistors of each hybrid circuit are arranged to maintain information or a control signal when provided with a supply voltage of a level that is higher than the idle level;

wherein each flip-flop of the multiple flip-flops comprises a majority of the high-threshold transistors and a minority of the low-threshold transistors; and

wherein each flip-flop of the multiple flip-flops comprises a pair of latches, wherein only one latch of the pair of latches comprises at least one low-threshold transistor.

2. The electronic circuit according to claim 1 , wherein the control signal providing circuit is arranged to provide a control signal that is an alternating clock signal to the multiple flip-flops, when the module is in the functional mode; and

wherein said control signal providing circuit is arranged to provide to the multiple flip-flops a fixed value clock signal that prevents the state change of each of the multiple flip-flops when the module is in the idle mode.

3. The electronic circuit according to claim 1 , wherein the control signal providing circuit is arranged to reset at least one flip-flop of the multiple flip-flops, when the module is in the functional mode; and

wherein said control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the idle mode, a reset signal of a value that prevents the multiple flip-flops from being reset.

4. The electronic circuit according to claim 1 , wherein the control signal providing circuit is arranged to set at least one flip-flop, when the module is in the functional mode; and

wherein said control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the idle mode, a set signal of a value that prevents the multiple flip-flops from being set.

5. A method for operating a module in a functional mode and in a idle mode, the method comprising:

determining whether the module should enter the functional mode or should enter the idle node;

when the module should enter the idle mode:

providing to the module a supply voltage of an idle level;

maintaining information stored in hybrid circuits of multiple flip-flops of the module; wherein each hybrid circuit comprises a low-threshold transistor that is coupled in parallel to at least one high-threshold transistor;

providing to the multiple flip-flops, by a control signal providing circuit that comprises at least one hybrid circuit, a control signal that prevents a state change of each of the multiple flip-flops;

wherein high-threshold transistors of each hybrid circuit are arranged to maintain information or a control signal when provided with a supply voltage of a level that is higher than the idle level;

when the module should enter the functional mode:

providing to the module a supply voltage of a functional level;

operating the module in the functional mode, wherein the operating of the module in the functional mode comprises:

utilizing at least a portion of the information stored in the hybrid circuits of the multiple flip-flops during the idle mode, and

providing to the multiple flip-flops a control signal that facilitates a state change of each of the multiple flip-flops; and

wherein each flip-flop of the multiple flip-flops comprise a pair of latches, wherein only one latch of the pair of latches comprises at least one low-threshold transistor.

6. The method according to claim 5 , comprising maintaining information stored in hybrid circuits that belong to a single latch out of a pair of latches of each flip-flop.

7. The method according to claim 5 , comprising providing to the multiple flip-flops the control signal that prevents a state change of each of the multiple flip-flops by a control signal providing circuit that comprises hybrid circuits that comprise low-threshold transistors and high-threshold transistors and are arranged to maintain a level of the control signal when the module is in the idle mode.

8. The method according to claim 5 , comprising:

providing to the multiple flip-flops, when the module is in the functional mode, a control signal that is an alternating clock signal; and

providing to the multiple flip-flops, when the module is in the idle mode, a fixed value clock signal that prevents the state change of each of the multiple flip-flops.

9. The method according to claim 5 , comprising:

providing to at least one flip-flop, when the module is in the functional mode, a control signal that is a reset signal of a value that resets the at least one flip-flop; and

providing to the multiple flip-flops, when the module is in the idle mode, a reset signal of a value that prevents the multiple flip-flops from being reset.

10. The method according to claim 5 , wherein each flip-flop of the multiple flip-flops comprises a majority of the high-threshold transistors and a minority of the low-threshold transistors.

11. An electronic circuit, comprising:

a module that comprises multiple flip-flops and a control signal providing circuit;

a power management circuit arranged to provide to the module a supply voltage of a functional level when the module is in a functional mode, and to provide to the module a supply voltage of an idle level when the module is in an idle mode;

wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the functional mode, a control signal that facilitates a state change of each of the multiple flip-flops;

wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the idle mode, a control signal that prevents a state change of each of the multiple flip-flops;

wherein each of the control signal providing circuit and a plurality of flip-flops of the multiple flip-flops comprises at least one hybrid circuit that comprises a low-threshold transistor that is coupled in parallel to at least one high-threshold transistor;

wherein each hybrid circuit is arranged to maintain information or a control signal when provided with the supply voltage of the idle level;

wherein high-threshold transistors of each hybrid circuit are arranged to maintain information or a control signal when provided with a supply voltage of a level that is higher than the idle level;

wherein each flip-flop of the multiple flip-flops comprises a pair of latches; and

wherein only one latch of the pair of latches comprises at least one low-threshold transistor.

12. The electronic circuit according to claim 11 , wherein the control signal providing circuit is arranged to reset at least one flip-flop of the multiple flip-flops, when the module is in the functional mode.

13. The electronic circuit according to claim 11 , wherein the control signal providing circuit is arranged to provide a control signal that is an alternating clock signal to the multiple flip-flops, when the module is in the functional mode; and

wherein said control signal providing circuit is arranged to provide to the multiple flip-flops a fixed value clock signal that prevents the state change of each of the multiple flip-flops when the module is in the idle mode.

14. The electronic circuit according to claim 11 , wherein the control signal providing circuit is arranged to reset at least one flip-flop of the multiple flip-flops, when the module is in the functional mode; and

wherein said control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the idle mode, a reset signal of a value that prevents the multiple flip-flops from being reset.

15. The electronic circuit according to claim 11 , wherein the control signal providing circuit is arranged to set at least one flip-flop, when the module is in the functional mode; and

wherein said control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the idle mode, a set signal of a value that prevents the multiple flip-flops from being set.

16. The electronic circuit according to claim 11 , wherein each flip-flop of the multiple flip-flops comprises a pair of latches, wherein each flip-flop is arranged to maintain information stored in hybrid circuits that belong to a single latch out of a pair of latches of each flip-flop.

17. The electronic circuit according to claim 1 , wherein each flip-flop of the multiple flip-flops comprises a pair of latches, wherein each flip-flop is arranged to maintain information stored in hybrid circuits that belong to a single latch out of a pair of latches of each flip-flop.

Assignments (27)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 17, 2018
From: NXP USA, INC.
To: VLSI TECHNOLOGY LLC
Reel/Frame 045084/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0334 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0285 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0387 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →