Patent Assignment
Reel/Frame 045084/0184
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2018-01-17
Received: 2018-01-17
Pages: 25
Assignor
NXP USA, INC.
Executed: 2017-12-04
Assignee
VLSI TECHNOLOGY LLC
1209 ORANGE STREET, WILMINGTON, DE, 19801, UNITED STATES
Covered Applications
(69)
INTEGRATED CIRCUIT, INTEGRATED CIRCUIT PACKAGE AND METHOD OF PROVIDING PROTECTION AGAINST AN ELECTROSTATIC DISCHARGE EVENT
App. No. 14/359,695
→
METHOD FOR PLACING OPERATIONAL CELLS IN A SEMICONDUCTOR DEVICE
App. No. 14/358,736
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INTEGRATED CIRCUIT DEVICE, VOLTAGE REGULATOR MODULE AND METHOD FOR COMPENSATING A VOLTAGE SIGNAL
App. No. 14/116,785
→
INTEGRATED CIRCUIT DEVICE AND METHOD OF ENABLING THERMAL REGULATION WITHIN AN INTEGRATED CIRCUIT DEVICE
App. No. 14/115,210
→
INTEGRATED CIRCUIT AND METHOD FOR REDUCING AN IMPACT OF ELECTRICAL STRESS IN AN INTEGRATED CIRCUIT
App. No. 14/006,388
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SWITCHING ARRANGEMENT, INTEGRATED CIRCUIT COMPRISING SAME, METHOD OF CONTROLLING A SWITCHING ARRANGEMENT, AND RELATED COMPUTER PROGRAM PRODUCT
App. No. 13/989,288
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ELECTRONIC CIRCUIT AND METHOD FOR STATE RETENTION POWER GATING
App. No. 13/634,730
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INTEGRATED CIRCUIT COMPRISING REFERENCE VOLTAGE GENERATION CIRCUITRY AND ELECTRONIC DEVICE
App. No. 13/511,321
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CONNECTION QUALITY VERIFICATION FOR INTEGRATED CIRCUIT TEST
App. No. 13/255,523
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COMPLEMENTARY BAND-GAP VOLTAGE REFERENCE CIRCUIT
App. No. 13/122,321
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BUS DRIVER FOR AVOIDING AN OVERVOLTAGE
App. No. 13/120,874
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MEMORY HAVING A LATCHING SENSE AMPLIFIER RESISTANT TO NEGATIVE BIAS TEMPERATURE INSTABILITY AND METHOD THEREFOR
App. No. 13/016,353
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INTEGRATED CIRCUIT DIE, AN INTEGRATED CIRCUIT PACKAGE AND A METHOD FOR CONNECTING AN INTEGRATED CIRCUIT DIE TO AN EXTERNAL DEVICE
App. No. 13/054,122
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SEMICONDUCTOR DEVICE AND METHOD OF ELECTROSTATIC DISCHARGE PROTECTION THEREFOR
App. No. 12/995,325
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DUAL PORT STATIC RANDOM ACCESS MEMORY CELL LAYOUT
App. No. 12/899,663
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PLL SYSTEM AND METHOD FOR CONTROLLING A GAIN OF A VCO CIRCUIT
App. No. 12/936,214
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PHASE CHANGE MEMORY STRUCTURES
App. No. 12/881,678
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ELECTRONIC CIRCUIT AND METHOD FOR OPERATING A MODULE IN A FUNCTIONAL MODE AND IN AN IDLE MODE
App. No. 12/850,650
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BAND-GAP VOLTAGE REFERENCE CIRCUIT HAVING MULTIPLE BRANCHES
App. No. 12/675,252
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MOLDED SEMICONDUCTOR PACKAGE HAVING A FILLER MATERIAL
App. No. 12/608,780
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PHASE LOCKED LOOP DEVICE AND METHOD THEREOF
App. No. 12/480,344
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METHOD FOR PROCESSING CDMA SIGNALS AND A DEVICE HAVING CDMA SIGNAL CAPABILITIES
App. No. 12/375,796
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METHOD AND APPARATUS FOR IMPROVEMENTS IN CHIP MANUFACTURE AND DESIGN
App. No. 12/375,854
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SEMICONDUCTOR FABRICATION PROCESS INCLUDING SILICIDE STRINGER REMOVAL PROCESSING
App. No. 12/244,413
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PROCESS OF USING A POLISHING APPARATUS INCLUDING A PLATEN WINDOW AND A POLISHING PAD
App. No. 12/243,543
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METHOD FOR GENERATING A OUTPUT CLOCK SIGNAL HAVING A OUTPUT CYCLE AND A DEVICE HAVING A CLOCK SIGNAL GENERATING CAPABILITIES
App. No. 12/179,826
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PHASE-LOCKED LOOP SYSTEM WITH A PHASE-ERROR SPREADING CIRCUIT
App. No. 12/180,166
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TESTING OF MULTIPLE INTEGRATED CIRCUITS
App. No. 12/130,173
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METHOD OF LOW POWER PLL FOR LOW JITTER DEMANDING APPLICATIONS
App. No. 12/041,687
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METHOD OF MAKING A VERTICAL PHASE CHANGE MEMORY (PCM) AND A PCM DEVICE
App. No. 12/039,371
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CLEANING SOLUTION FOR A SEMICONDUCTOR WAFER
App. No. 11/914,870
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PHASE CHANGE MEMORY STRUCTURES
App. No. 11/864,246
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PHASE CHANGE MEMORY STRUCTURES INCLUDING PILLARS
App. No. 11/864,257
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TESTER AND A METHOD FOR TESTING AN INTEGRATED CIRCUIT
App. No. 11/753,003
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LIGHT ERASABLE MEMORY AND METHOD THEREFOR
App. No. 11/620,075
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MEMORY WITH SHARED WRITE BIT LINE(S)
App. No. 11/619,808
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METHOD OF PACKAGING A DEVICE USING A DIELECTRIC LAYER
App. No. 11/561,241
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ENGINEERING STRAIN IN THICK STRAINED-SOI SUBSTRATES
App. No. 11/420,849
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MEMORY WITH CLOCKED SENSE AMPLIFIER
App. No. 11/392,402
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POLISHING PAD, A POLISHING APPARATUS, AND A PROCESS FOR USING THE POLISHING PAD
App. No. 11/390,176
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METHOD OF FORMING DEVICE HAVING A RAISED EXTENSION REGION
App. No. 11/324,510
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SIGNAL CONVERTERS WITH MULTIPLE GATE DEVICES
App. No. 11/250,993
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SEMICONDUCTOR DEVICE HAVING NANO-PILLARS AND METHOD THEREFOR
App. No. 11/244,516
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METHOD OF MAKING A MULTI-BIT NON-VOLATILE MEMORY (NVM) CELL AND STRUCTURE
App. No. 11/240,242
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PROCESS OF MAKING A III-V COMPOUND SEMICONDUCTOR HETEROSTRUCTURE MOSFET
App. No. 11/236,186
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III-V COMPOUND SEMICONDUCTOR HETEROSTRUCTURE MOSFET DEVICE
App. No. 11/236,185
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SEMICONDUCTOR FABRICATION PROCESS INCLUDING SILICIDE STRINGER REMOVAL PROCESSING
App. No. 11/226,826
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GROOVED PLATEN WITH CHANNELS OR PATHWAY TO AMBIENT AIR
App. No. 11/221,375
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INTEGRATED CIRCUIT WITH MULTIPLE INDEPENDENT GATE FIELD EFFECT TRANSISTOR (MIGFET) RAIL CLAMP CIRCUIT
App. No. 11/130,873
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PROCESSES FOR FORMING ELECTRONIC DEVICES INCLUDING NON-VOLATILE MEMORY
App. No. 11/084,283
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INTEGRATION OF MULTIPLE GATE DIELECTRICS BY SURFACE PROTECTION
App. No. 10/962,944
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DEVICE AND A METHOD FOR BIASING A TRANSISTOR THAT IS CONNECTED TO A POWER CONVERTER
App. No. 10/955,219
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MRAM SENSE AMPLIFIER HAVING A PRECHARGE CIRCUIT AND METHOD FOR SENSING
App. No. 10/943,579
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METHOD AND APPARATUS UTILIZING MONOCRYSTALLINE INSULATOR
App. No. 10/861,467
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AUTOMATIC HIDDEN REFRESH IN A DRAM AND METHOD THEREFOR
App. No. 10/854,298
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STATE RETENTION WITHIN A DATA PROCESSING SYSTEM
App. No. 10/818,861
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ARRANGEMENT AND METHOD FOR ESD PROTECTION
App. No. 10/651,128
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MULTIBIT ROM CELL AND METHOD THEREFOR
App. No. 10/640,723
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BODY-TIED SILICON ON INSULATOR SEMICONDUCTOR DEVICE AND METHOD THEREFOR
App. No. 10/462,178
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SEMICONDUCTOR PACKAGE HAVING OPTIMIZED WIRE BOND POSITIONING
App. No. 10/457,632
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ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING SAME
App. No. 10/367,344
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SENSE AMPLIFIER BIAS CIRCUIT FOR A MEMORY HAVING AT LEAST TWO DISTINCT RESISTANCE STATES
App. No. 10/283,622
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NON-VOLATILE MEMORY DEVICE HAVING AN ANTI-PUNCH THROUGH (APT) REGION
App. No. 10/267,199
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NON-VOLATILE MEMORY DEVICE AND METHOD FOR FORMING
App. No. 10/267,153
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PROCESS FOR DEPOSITING A LAYER OF MATERIAL ON A SUBSTRATE AND A PLATING SYSTEM
App. No. 10/218,810
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HYSTERESIS REDUCED SENSE AMPLIFIER AND METHOD OF OPERATION
App. No. 10/027,547
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METHOD OF FORMING BODY-TIED SILICON ON INSULATOR SEMICONDUCTOR DEVICE
App. No. 10/024,916
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METHOD FOR FORMING A SEMICONDUCTOR DEVICE FOR DETECTING LIGHT
App. No. 09/990,977
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Method and apparatus utilizing monocrystalline insulator
App. No. 09/978,096
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