Signal converters with multiple gate devices
View Patent ↗An analog to digital converter including a plurality of multiple independent gate field effect transistors (MIGFET) that provide a plurality of digital output signals, is provided. Each MIGFET of the plurality of MIGFETs may have first gate for receiving an analog signal, a second gate for being biased, and a current electrode for providing a digital output signal from among the plurality of the digital output signals. Each MIGFET of the plurality of MIGFETs may have a combination of body width, channel length that is unique among the plurality of MIGFETs to result in a threshold voltage that is unique among the plurality of MIGFETs. A digital to analog converter including a plurality of MIGFETs is also provided.
1. An analog to digital converter comprising:
a plurality of multiple independent gate FETs (MIGFETs) that provides a plurality of digital output signals, wherein
each MIGFET of the plurality of MIGFETs has a first gate for receiving an analog signal, a second gate for being biased, and a current electrode for providing a digital output signal from among the plurality of the digital output signals; and
each MIGFET of the plurality of MIGFETs has a combination of body width and channel length that is unique among the plurality of MIGFETs to result in a threshold voltage that is unique among the plurality of MIGFETs.
2. The analog to digital converter of claim 1 , wherein the plurality of MIGFETs comprises:
a first MIGFET having a first body width and a first channel length;
a second MIGFET having a second body width and a second channel length;
a third MIGFET having a third body width and a third channel length; and
a fourth MIGFET having a fourth body width and a fourth channel length.
3. The analog to digital converter of claim 1 , wherein each of the MIGFETS of the plurality of MIGFETs is further characterized as having a second current electrode coupled to a ground terminal.
4. The analog to digital converter of claim 1 further comprising a bias circuit coupled to each of the second gates of the plurality of MIGFETs.
5. The analog to digital converter of claim 4 , wherein the bias circuit provides a bias voltage that alters the threshold voltage of each of the MIGFETs of the plurality of MIGFETs.
6. The analog to digital converter of claim 5 , wherein the bias circuit is further characterized as being programmable.
7. The analog to digital converter of claim 1 , wherein the MIGFETs are further characterized as being N channel.
8. An analog to digital converter comprising:
a plurality of FETs that provides a plurality of digital output signals, wherein the plurality of FETS comprising a plurality of MIGFETs, and wherein
each FET of the plurality of FETs has a first gate for receiving an analog signal and a current electrode for providing a digital output signal of a plurality of the digital output signals; and
each FET of the plurality of FETs has a threshold voltage that is unique among the plurality of FETs.
9. The analog to digital converter of claim 8 , wherein the plurality of MIGFETs have at least four different body widths.
10. The analog to digital converter of claim 9 , wherein the plurality of MIGFETs have at least four different channel lengths.
11. The analog to digital converter of claim 10 , further comprising a programmable bias circuit, wherein each MIGFET of the plurality of MIGFETs has a second gate coupled to the programmable bias circuit to alter the threshold voltage of each of the MIGFETs of the plurality of MIGFETs.
12. The analog to digital converter of claim 11 , further comprising load devices coupled to the current electrodes of the MIGFETs, wherein the load devices comprise MIGFETs that have tunable impedances.
13. A digital to analog converter, comprising:
a plurality of FETs that provides an analog signal at a summing node, wherein the plurality of FETS comprising a plurality of MIGFETs, and wherein
each FET of the plurality of FETs has a first gate for receiving a different digital signal from among a plurality of digital signals, and a current electrode coupled to the summing node; and
each FET of the plurality of FETs has a threshold voltage that is unique among the plurality of FETs.
14. The digital to analog converter of claim 13 , wherein the plurality of MIGFETs have at least four different body widths.
15. The digital to analog converter of claim 14 , wherein the plurality of MIGFETs have at least four different channel lengths.
16. The digital to analog converter of claim 15 , wherein each MIGFET of the plurality of MIGFETs has a second gate for being biased to alter the threshold voltage of each of the MIGFETs of the plurality of MIGFETs.
17. The digital to analog converter of claim 16 , further comprising a programmable bias circuit coupled to the second gates of the plurality of MIGFETs.
18. The digital to analog converter of claim 13 , further comprising a current to voltage converter coupled to the summing node.