Systems and methods for configuring load/store execution units
View Patent ↗Systems and methods are disclosed for multi-threading computer systems. In a computer system executing multiple program threads in a processing unit, a first load/store execution unit is configured to handle instructions from a first program thread and a second load/store execution unit is configured to handle instructions from a second program thread. When the computer system executing a single program thread, the first and second load/store execution units are reconfigured to handle instructions from the single program thread, and a Level 1 (L1) data cache is reconfigured with a first port to communicate with the first load/store execution unit and a second port to communicate with the second load/store execution unit.
1. A method comprising:
in a computer system executing multiple program threads in a processing unit:
configuring a first load/store execution unit to handle instructions from a first program thread;
configuring a second load/store execution unit to handle instructions from a second program thread;
in the computer system executing a single program thread in the processing unit:
configuring the first and second load/store execution units to handle instructions from the single program thread;
configuring a Level 1 (L1) data cache with a first port to communicate with the first load/store execution unit and a second port to communicate with the second load/store execution unit;
adding a second tag array for the first L1 data cache, wherein the first load/store execution unit uses a first tag array to access the first L1 data cache and the second load/store execution unit uses the second tag array to access the first L1 data cache;
for every load/store instruction from the first and second load/store execution units, maintaining duplicate data and address information in a first load/store buffer associated with the first load/store execution unit and in a second load/store buffer associated with the second load/store execution unit.
2. The method of claim 1 further comprising:
in single thread mode, detecting address conflicts between instructions from the first load/store execution unit and instructions from the second load/store execution unit.
3. The method of claim 2 further comprising:
in single thread mode, when an address conflict arises during a same processor clock cycle, delaying execution of one of the instructions.
4. The method of claim 1 further comprising:
in single thread mode, configuring two decode/issue units to issue two instructions to a first load/store execution queue and one decode/issue unit to one instruction to a second load/store execution queue.
5. The method of claim 1 further comprising:
in single thread mode,
configuring the first load/store execution unit with a first load/store buffer;
configuring the second load/store execution unit with a second load/store buffer; and
writing data into the first and second load/store buffers for every load/store instruction from the first and second load/store execution units.
6. The method of claim 1 further comprising:
in single thread mode,
writing any data updates to a memory management unit (MMU) to both a first MMU and a second MMU.
7. The method of claim 1 further comprising:
in single thread mode,
reconfiguring a second L1 data cache as a victim cache for the first L1 data cache.
8. A microprocessor system comprising:
a first L1 data cache;
a second L1 data cache;
a first load/store execution unit;
a second load/store execution unit;
a first load/store buffer coupled to the first load/store execution unit;
a second load/store buffer coupled to the second load/store execution unit;
a conflict resolution unit;
a first MMU associated with the first L1 data cache;
a second MMU associated with the second L1 data cache;
when the system is configured for a multi-thread mode,
a first program thread accesses the first load/store execution unit;
a second program thread accesses the second load/store execution unit;
the first load/store execution unit accesses the first L1 data cache;
the second load/store execution unit accesses the second L1 data cache; and
when the system is configured for a single-thread mode,
a single program thread accesses the first and second load/store execution units, and the first and second load/store units access the first L1 data cache;
the conflict resolution unit delays execution of an instruction from the second load/store execution unit when an address conflict with an instruction from the first load/store execution unit is detected;
any first and second L1 data cache updates are written to both the first MMU and the second MMU; and
load/store data is written into the first and second load/store buffers for every load/store instruction from the first and second load/store instruction units.
9. The system of claim 8 further comprising:
when the system is configured for the single thread mode,
a first tag array for the first L1 data cache;
a second tag array for the first L1 data cache, wherein the first load/store execution unit uses the first tag array to access the first L1 data cache and the second load/store execution unit uses the second tag array to access the first L1 data cache.
10. The system of claim 8 further comprising:
when the system is configured for a single-thread mode,
a second L1 data cache is configured as a victim cache for the first L1 data cache.
11. A processing system comprising:
a first load/store execution unit including first load/store buffers;
a second load/store execution unit including second load/store buffers;
a first data cache;
logic instructions executable to:
determine a number of program threads executing in the processing system; and
when a single program thread is executing,
maintain identical load/store buffers for the first and second load/store execution units,
access a first bank in the first data cache via a first port for instructions from the first load/store execution unit, and
access a second bank in the first data cache via a second port for instructions from the second load/store execution unit.
12. The system of claim 11 further comprising:
a conflict resolution unit; and
when the system is configured for the single thread mode, the conflict resolution unit delays execution of an instruction from the second load/store execution unit when an address conflict is detected.
13. The system of claim 11 further comprising:
when the system is configured for the single thread mode, any data updates to a memory management unit (MMU) are written to both a first MMU and a second MMU.
14. The system of claim 13 further comprising:
a first MMU coupled to the first L1 data cache;
a second MMU coupled to the first L1 data cache;
when the system is configured for the single thread mode,
data is written into the first and second MMUs for every load/store instruction from the first and second load/store execution units.
15. The system of claim 14 further comprising:
when the system is configured for the single thread mode,
a first tag array for the first L1 data cache;
a second tag array for the first L1 data cache, wherein the first load/store execution unit uses the first tag array to access the first L1 data cache and the second load/store execution unit uses the second tag array to access the first L1 data cache.
16. The system of claim 11 further comprising:
when the system is configured for a single-thread mode,
a second L1 data cache is configured as a victim cache for the first L1 data cache.