Non-volatile memory and logic circuit process integration
View Patent ↗A method for forming an integrated circuit for a non-volatile memory cell transistor is disclosed that includes: forming a layer of discrete storage elements over a substrate in a first region of the substrate and in a second region of the substrate; forming a first layer of dielectric material over the layer of discrete storage elements in the first region and the second region; forming a first layer of barrier work function material over the first layer of dielectric material in the first region and the second region; and removing the first layer of barrier work function material from the second region, the first layer of dielectric material from the second region, and the layer of discrete storage elements from the second region. After the removing, a second layer of barrier work function material is formed over the substrate in the first region and the second region. The second layer of barrier work function material is removed from the first region. A first gate of a memory device is formed in the first region. The first gate includes a portion of the first layer of barrier work function material. The memory device includes a charge storage structure including a portion of the layer of discrete storage elements. A second gate of a transistor is formed in the second region, the second gate including a portion of the second layer of barrier work function material.
1. A method of forming an integrated circuit comprising:
forming a layer of discrete storage elements over a substrate in a first region of the substrate and in a second region of the substrate;
forming a first layer of dielectric material over the layer of discrete storage elements in the first region and the second region;
forming a first layer of barrier work function material over the first layer of dielectric material in the first region and the second region;
removing the first layer of barrier work function material from the second region, the first layer of dielectric material from the second region, and the layer of discrete storage elements from the second region;
after the removing, forming a second layer of barrier work function material over the substrate in the first region and the second region;
removing the second layer of barrier work function material from the first region;
forming a first gate of a memory device in the first region, the first gate includes a portion of the first layer of barrier work function material, the memory device includes a charge storage structure including a portion of the layer of discrete storage elements;
forming a second gate of a transistor in the second region, the second gate including a portion of the second layer of barrier work function material.
2. The method of claim 1 wherein the first layer of dielectric material is a layer of high-k dielectric material.
3. The method of claim 1 after the removing the first layer of barrier work function material from the second region, the first layer of dielectric material from the second region, and the layer of discrete storage elements from the second region and before forming the second layer of barrier work function material, forming a second layer of dielectric material over the substrate in the first region and the second region.
4. The method of claim 3 wherein after the removing the second layer of barrier work function material from the first region, removing the second layer of dielectric material from the first region, wherein the first layer of barrier work function material protects the first layer of dielectric material in the first region during the removing the second layer of dielectric material.
5. The method of claim 3 wherein the second layer of dielectric material is a layer of high-k dielectric material.
6. The method of claim 1 wherein the removing the first layer of barrier work function material from the second region, the first layer of dielectric material from the second region, and the layer of discrete storage elements from the second region includes forming a layer of patterned photo resist over the first layer of barrier work function material in the first region.
7. The method of claim 1 , further comprising:
after the removing the second layer of barrier work function material from the first region, forming a first layer of gate material over the substrate in the first region and the second region.
8. The method of claim 7 wherein the first gate of the memory device includes a first portion of the first layer of gate material, and the second gate of the transistor includes a second portion of the first layer of gate material.
9. The method of claim 8 wherein a resistivity of the first layer of gate material is lower than a resistivity of the first layer of barrier work function material and a resistivity of the second layer of barrier work function material.
10. The method of claim 1 further comprising:
before the forming a layer of discrete storage elements, forming a first layer of gate material over the substrate in the first region of the substrate and in the second region of the substrate; and
patterning the first layer of gate material to form a first sidewall in the first region.
11. The method of claim 10 wherein the patterning the first layer of gate material removes the first layer of gate material from the second region.
12. The method of claim 10 wherein the memory device includes a third gate including material of the first layer of gate material.
13. The method of claim 12 wherein the first gate is characterized as a control gate for the memory device and the third gate is characterized as a select gate of a memory device.
14. The method of claim 1 wherein the discrete storage elements of the layer of discrete storage elements are characterized as silicon nanocrystals.
15. The method of claim 1 wherein the first layer of barrier work function material and the second layer of barrier work function material each include tantalum nitride.
16. The method of claim 1 further comprising:
after the removing the second layer of barrier work function material from the first region, forming a third layer of barrier work function material over the substrate in the first region, in the second region, and in a third region of the substrate, wherein the second layer of barrier work function material has been removed from the third region;
removing the third layer of barrier work function material from the first region and the second region;
forming a third gate of a second transistor in the third region, wherein the third gate includes a portion of the third layer of barrier work function material.
17. A method of making an integrated circuit comprising:
forming a first layer of gate material over a substrate in the first region of the substrate and in the second region of the substrate;
patterning the first layer of gate material to form a first sidewall in the first region;
after the patterning, forming a layer of discrete storage elements over the substrate in the first region and the second region;
forming a first layer of high-k dielectric material over the layer of discrete storage elements in the first region and the second region;
forming a first layer of barrier work function material over the first layer of high-k dielectric material in the first region and the second region;
removing the first layer of barrier work function material from the second region, the layer of discrete storage elements from the second region, and the first layer of high-k dielectric material from the second region;
after the removing, forming a second layer of barrier work function material over the substrate in the first region and the second region;
removing the second layer of barrier work function material from the first region;
forming a first gate of a memory device in the first region, the first gate includes a portion of the first layer of barrier work function material, the memory device includes a charge storage structure including a portion of the discrete storage elements, the memory device including a second gate including a portion of the first layer of gate material;
forming a third gate of a transistor in the second region, the third gate including a portion of the second layer of barrier work function material.
18. The method of claim 17 further comprising:
forming a second layer of high-k dielectric material in the first region and the second region, wherein the second layer of barrier work function material is formed over the second layer of high-k dielectric material in the first region and the second region;
removing the second layer of high-k dielectric material from the first region after the removing the second layer of barrier work function material from the first region, wherein the first layer of barrier work function material protects the first layer of high-k dielectric material in the first region during the removing the second layer of high-k dielectric material.
19. The method of claim 17 wherein the discrete storage elements of the layer of discrete storage elements are characterized as nanocrystals formed from silicon.
20. The method of claim 17 , further comprising:
after the removing the second layer of barrier work function material from the first region, forming a second layer of gate material over the substrate in the first region and the second region, wherein the first gate and the third gate each include a portion of the second layer of gate material.