Data processing system operable in single and multi-thread modes and having multiple caches and method of operation
View Patent ↗Systems and methods are disclosed for a computer system that includes a first load/store execution unit 210 a , a first Level 1 L1 data cache unit 216 a coupled to the first load/store execution unit, a second load/store execution unit 210 b , and a second L1 data cache unit 216 b coupled to the second load/store execution unit. Some instructions are directed to the first load/store execution unit and other instructions are directed to the second load/store execution unit when executing a single thread of instructions.
1. A method comprising:
in a computer system including a first load/store execution unit, a first Level 1 (L1) data cache unit coupled to the first load/store execution unit, a second load/store execution unit, and a second L1 data cache unit coupled to the second load/store execution unit, the method comprises:
directing some instructions to the first load/store execution unit and other instructions to the second load/store execution unit when executing a single thread of instructions, wherein each directed instruction is directed to one of the first or the second load/store execution units based on a characteristic of a register number which holds a base address of the load/store instruction or based on one or more prediction bits associated with the register number which holds the base address of the load/store instruction, wherein the one or more prediction bits indicate one of the first or second load/store execution units;
dispatching a current load or store instruction to a selected load execution queue;
if the current load or store instruction is selected for execution, accessing a selected one of the first and second L1 data cache units;
determining if there is a cache hit in the selected one of the first and second L1 data cache units; and
when there is no cache hit in the selected one of the first and selected L1 data cache units, determining if there is a cache hit in the one of the first and second L1 data cache units that was not selected.
2. The method of claim 1 further comprising:
alternately directing the load and store instructions to the first load store execution unit and to the second load/store execution unit; and
setting up base register prediction based on selection of the first load store execution unit or the second load store execution unit.
3. The method of claim 1 further comprising:
an array of share indicators corresponding to the first L1 data cache unit that indicate whether a cache line is shared with another cache; and
an array of location indicators that point to the shared cache line in the other cache.
4. The method of claim 3 further comprising:
prior to dispatching the current load or store instruction to the selected load execution queue, checking dependency between a current load or store instruction with instructions in load execution queues.
5. The method of claim 4 further comprising:
when the current load or store instruction is a load instruction and there is no cache hit in the selected one of the first and second L1 data cache units,
when there is not a cache hit in the one of the first and second L1 data cache units that was not selected,
fetching a cache line from Level 2 (L2) data cache to write into the selected one of the first and second L1 data cache units, and
when there is a cache hit in the one of the first and second L1 data cache units that was not selected,
fetching data from the one of the first and second L1 data cache units that was not selected,
when the first and second L1 data cache units are in write-through mode,
setting a share indicator and location indicator of the one of the first and second L1 data cache units that was not selected for the one of the first and second L1 data cache units that was selected,
when the first and second L1 data cache units are in copy-back mode,
canceling the request for cache data to the L2 data cache unit,
setting the share indicator and the location indicator of the one of the first and second L1 data cache units that was not selected for the one of the first and second L1 data cache units that was selected, and
fetching a cache line and control indicators from the one of the first and second L1 data cache units that was not selected to write into the one of the first and second L1 data cache units that was selected.
6. The method of claim 4 further comprising:
when the current load or store instruction is a store instruction and there is no cache hit in the selected one of the first and second L1 data cache units,
when there is not a cache hit in the one of the first and second L1 data cache units that was not selected,
sending a request to write store data to L2 data cache,
when there is a cache hit in the one of the first and second L1 data cache units that was not selected,
writing the store data in the one of the first and second L1 data cache units that was not selected,
when the one of the first and second L1 data cache units that was not selected is in copy-back mode, initializing cache control indicators; and
when there is a cache hit in the one of the first and second L1 data cache units that was selected,
writing the store data in the one of the first and second L1 data cache units that was selected,
at the same time that the store data is being written, invalidating an entry of the one of the first and second L1 data cache units if the share indicator is set,
when the one of the first and second L1 data cache units that was selected is in copy-back mode, initializing cache control indicators, and
when the one of the first and second L1 data cache units that was selected is in write-through mode, sending a request to write store data to L2 data cache.
7. The method of claim 1 further comprising:
prior to dispatching the current load or store instruction to the selected execution queue, looking up prediction indicators for a base address register number for one of the load or store instructions, directing the load or store instruction to a selected one of the first load store execution unit and a second load/store execution unit, and checking dependency between a current load or store instruction with instructions in load execution queues;
when the current load or store instruction is a load instruction and there is no cache hit in the selected one of the first and second L1 data cache units,
when there is not a cache hit in the one of the first and second L1 data cache units that was not selected,
fetching a cache line from L2 data cache to write into the selected one of the first and second L1 data cache units, and
when there is a cache hit in the one of the first and second L1 data cache units that was not selected,
fetching data from the one of the first and second L1 data cache units that was not selected,
canceling the request to the L2 cache, and
modifying prediction indicators for a base address register number.
8. The method of claim 7 further comprising:
when the current load or store instruction is a store instruction and there is no cache hit in the selected one of the first and second L1 data cache units,
when there is not a cache hit in the one of the first and second L1 data cache units that was not selected,
sending a request to write store data to L2 data cache,
when there is a cache hit in the one of the first and second L1 data cache units that was not selected,
writing the store data in the one of the first and second L1 data cache units that was not selected, and
modifying prediction indicators for a base address register number,
when the one of the first and second L1 data cache units that was not selected is in copy-back mode, initializing cache control indicators, and
when the one of the first and second L1 data cache units that was not selected is in write-through mode, sending a request to write store data to Level 2 L2 data cache.
9. The method of claim 7 further comprising:
when there is a cache hit in the one of the first and second L1 data cache units that was selected,
writing the store data in the one of the first and second L1 data cache units that was selected,
when the one of the first and second L1 data cache units that was selected is in copy-back mode, initializing cache control indicators, and
when the one of the first and second L1 data cache units that was selected is in write-through mode, sending a request to write store data to L2 data cache.
10. A microprocessor system comprising:
a first load/store execution unit;
a first L1 data cache unit coupled to the first load/store execution unit;
a second load/store execution unit;
a second L1 data cache unit coupled to the second load/store execution unit, wherein the first load/store execution unit and the first L1 data cache operate independently of the second load/store execution unit and the second L1 data cache unit; and
a plurality of decode/issue units configured to specify the first load/store execution unit and the second load/store execution unit when executing a single thread of instructions based on steering logic that directs load and store instructions for the single thread to the first load/store execution unit or the second load/store execution unit, wherein each load and store instruction for the single thread is directed by the steering logic to one of the first or the second load/store execution units based on a characteristic of a register number which holds a base address of the load/store instruction or based on one or more prediction bits associated with the register number which holds the base address of the load/store instruction, wherein the one or more prediction bits indicate one of the first or second load/store execution units, wherein the plurality of decode/issue units are further configured to dispatch a current load or store instruction to a selected load execution queue;
a load/store arbiter configured to select the current load or store instruction for execution, wherein a selected one of the first and second L1 data cache units is configured to determine if there is a cache hit for the current load or store instruction, and the one of the first and second L1 data cache units that was not selected is configured to, when there is no cache hit in the selected one of the first and second L1 data cache units, determine if there is a cache hit for the current load or store instruction.
11. The system of claim 10 further comprising:
an array of share indicators corresponding to the first L1 data cache unit that indicate whether a cache line is shared with another cache; and
an array of location indicators that point to the shared cache line in the other cache.
12. The system of claim 11
wherein the plurality of decode/issue units are configured to check dependency between a current load or store instruction with instructions in load execution queues prior to dispatching the current load or store instruction to the selected load execution queue.
13. The system of claim 12
wherein the L1 data cache units are configured to
when the current load or store instruction is a load instruction and there is no cache hit in the selected one of the first and second L1 data cache units,
when there is not a cache hit in the one of the first and second L1 data cache units that was not selected,
fetch a cache line from L2 data cache to write into the selected one of the first and second L1 data cache units, and
when there is a cache hit in the one of the first and second L1 data cache units that was not selected, fetch data from the one of the first and second L1 data cache units that was not selected; and
when there is a cache hit in the one of the first and second L1 data cache units that was not selected,
when the first and second L1 data cache units are in write-through mode,
set a share indicator and a location indicator of the one of the first and second L1 data cache units that was not selected for the one of the first and second L1 data cache units that was selected,
when the first and second L1 data cache units are in copy-back mode,
cancel the request for cache data to the L2 data cache units,
set a share indicator and a location indicator of the one of the first and second L1 data cache units that was not selected for the one of the first and second L1 data cache units that was selected, and
fetch a cache line and control indicators from the one of the first and second L1 data cache units that was not selected to write into the one of the first and second L1 data cache units that was selected.
14. The system of claim 12
wherein the L1 data cache units are configured to
when the current load or store instruction is a store instruction and there is no cache hit in the selected one of the first and second L1 data cache units,
when there is not a cache hit in the one of the first and second L1 data cache units that was not selected,
send a request to write store data to L2 data cache,
when there is a cache hit in the one of the first and second L1 data cache units that was not selected,
write the store data in the one of the first and second L1 data cache units that was not selected, and
when the one of the first and second L1 data cache units that was not selected is in copy-back mode, initialize cache control indicators; and
when there is a cache hit in the one of the first and second L1 data cache units that was selected,
write the store data in the one of the first and second L1 data cache units that was selected,
at the same time that the store data is being written, invalidate an entry of the one of the first and second L1 data cache units if the share indicator is set,
when the one of the first and second L1 data cache units that was selected is in copy-back mode, initialize cache control indicators, and
when the one of the first and second L1 data cache units that was selected is in write-through mode, send a request to write store data to L2 data cache.
15. The system of claim 10 wherein the steering logic
alternately directing the load and store instructions to the first load store execution unit and to the second load/store execution unit; and
setting up base register prediction based on selection of the first load store execution unit or the second load store execution unit.
16. The system of claim 10
wherein the plurality of decode/issue units are configured to, prior to dispatching the current load or store instruction to the selected load execution queue, look up prediction indicators for a base address register number for one of the load or store instructions, direct the load or store instruction to a selected one of the first load store execution unit and a second load/store execution unit, and check dependency between a current load or store instruction with instructions in load execution queues.
17. The system of claim 16
wherein the L1 data cache units are configured to
when the current load or store instruction is a load instruction and there is no cache hit in the selected one of the first and second L1 data cache units,
when there is not a cache hit in the one of the first and second L1 data cache units that was not selected,
fetch a cache line from L2 data cache to write into the selected one of the first and second L1 data cache units, and
when there is a cache hit in the one of the first and second L1 data cache units that was not selected,
fetch data from the one of the first and second L1 data cache units that was not selected,
cancel the request to the L2 cache, and
modify prediction indicators for a base address register number.
18. The system of claim 16
wherein the L1 data cache units are configured to
when the current load or store instruction is a store instruction and there is no cache hit in the selected one of the first and second L1 data cache units,
when there is not a cache hit in the one of the first and second L1 data cache units that was not selected,
send a request to write store data to L2 data cache,
when there is a cache hit in the one of the first and second L1 data cache units that was not selected,
write the store data in the one of the first and second L1 data cache units that was not selected, and
modify prediction indicators for a base address register number,
when the one of the first and second L1 data cache units that was not selected is in copy-back mode, initialize cache control indicators, and
when the one of the first and second L1 data cache units that was not selected is in write-through mode, send a request to write store data to L2 data cache.
19. The system of claim 16
wherein the L1 data cache units are configured to
when there is a cache hit in the one of the first and second L1 data cache units that was selected,
write the store data in the one of the first and second L1 data cache units that was selected,
when the one of the first and second L1 data cache units that was selected is in copy-back mode, initialize cache control indicators, and
when the one of the first and second L1 data cache units that was selected is in write-through mode, send a request to write store data to L2 data cache.
20. A method comprising:
in a computer system including a first load/store execution unit, a first Level 1 (L1) data cache unit coupled to the first load/store execution unit, a second load/store execution unit, and a second L1 data cache unit coupled to the second load/store execution unit,
directing some load/store instructions to the first load/store execution unit and other load/store instructions to the second load/store execution unit when executing a single thread of instructions, wherein each load/store instruction is directed to one of the first or the second load/store execution units based on a characteristic of a register number which holds a base address of the load/store instruction.