IP Library Granted Patent US 8,482,099
Granted Patent B2
US 8,482,099 · App. 12/933,208 · Granted Jul 9, 2013

Poly-resistor, and linear amplifier

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Quick Facts
Patent No.
US 8,482,099
App. No.
12/933,208
Granted
Jul 9, 2013
Kind
B2
Abstract

The present invention provides a poly-resistor with an improved linearity. Majority charge carrier wells are provided under the poly-strips and are biased in such way that the non-linearity of the resistor is reduced. Further, when such poly-resistors are used in amplifier circuits, the gain of the amplifier remains constant against the poly-depletion effect.

Claims (28)

1. A poly-resistor, comprising:

a first region wherein the first region is characterized as semiconductive or conductive;

a resistive strip providing a resistive connection between a first resistor contact and a second resistor contact; said resistive strip extending over at least a part of said first region;

a dielectric layer isolating said first region from said resistive strip; and

a bias source connected to said first region, for biasing said first region to a voltage which lies between a voltage at the first resistor contact and a voltage at the second resistor contact, said bias source including:

a second resistive strip providing a resistive connection between a third resistor contact at which a first voltage can be applied and a forth resistor contact at which a second voltage can be applied; and

a conductive path from said second resistive strip to said first region, for biasing said first region with a bias voltage between said first voltage and said second voltage.

2. A poly-resistor as claimed in claim 1 , wherein said bias source includes a conductive path from said resistive strip to said first region.

3. A poly-resistor as claimed in claim 2 , wherein said conductive path includes: at least one passage through said dielectric layer that electrically connects a position at said resistive strip to said first region, said conductive path for biasing said first region to a voltage of said position.

4. A poly-resistor as claimed in claim 3 , wherein when said poly-resistor is in use, a first change in resistivity occurs in a part of said strip between said position and said first resistor contact and a second change in resistivity occurs in a part of said strip between said position and said second resistor contact, said second change at least partially compensating said first change.

5. A poly-resistor as claimed in claim 3 , wherein a distance between said position and said first resistor contact is substantially equal to a distance between said position and said second resistor contact.

6. A poly-resistor as claimed in claim 1 , wherein the first region is provided with an n-type doping and a material below the first region is provided with a p-type doping or vice versa.

7. A poly-resistor as claimed in claim 1 , wherein said dielectric layer is a shallow trench isolation region extending over said first region.

8. A poly-resistor as claimed in claim 1 , wherein said resistive strip is a poly-silicon strip.

9. A poly-resistor as claimed in claim 1 , wherein the sheet resistance of the poly-resistor is in a range of 10Ω to 10 kΩ per square.

10. A poly-resistor as claimed in claim 1 , wherein said resistive strip has a rectangular shape and wherein said first resistor contact is provided at a first end of the rectangular shape and the second resistor contact is provided at a second end of the rectangular shape, opposite to the first edge.

11. A poly-resistor as claimed in claim 10 , wherein a conductive element is provided, in a direction from the first end to the second end, in the middle of said rectangular shape.

12. A poly-resistor as claimed in claim 11 , wherein said conductive element separates said resistive strip into a first part and a second part and is connected to said first region.

13. A poly-resistor as claimed in claim 1 , including a substrate and, optionally at least one intermediate layer between said substrate and said dielectric layer, and wherein said first region is provided in said substrate and/or at least one of said at least one intermediate layer.

14. An integrated circuit including a poly-resistor as claimed in claim 1 .

15. An amplifier circuit comprising:

an input for receiving input signal;

an amplifying stage including a stage input and a stage output;

a poly-resistor connected to said stage input and/or said output: and

an output connected to said stage output, for outputting an amplified signal; wherein the poly-resistor is a poly-resistor as claimed in claim 1 .

16. A poly-resistor as claimed in claim 4 , wherein a distance between said position and said first resistor contact is substantially equal to a distance between said position and said second resistor contact.

17. A poly-resistor as claimed in claim 2 , wherein the first region is provided with an n-type doping and a material below the first region is provided with a p-type doping or vice versa.

18. A poly-resistor as claimed in claim 7 wherein said resistive strip is a poly-silicon strip.

Assignments (25)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
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From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
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CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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SECURITY AGREEMENT Recorded Nov 6, 2013
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