Using built-in self test for preventing side channel security attacks on multi-processor systems
View Patent ↗A data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the second processor which performs BIST memory accesses on the local memory of the second processor and which includes a random value generator is provided. The system can perform a method including executing a secure code sequence by the first processor and performing, by the BIST controller of the second processor, BIST memory accesses to the local memory of the second processor in response to the random value generator. Performing the BIST memory accesses is performed concurrently with executing the secure code sequence.
1. A data processing system, comprising:
a first processor;
a second processor, the second processor having a cache;
a built-in self-test (BIST) controller coupled to the cache of the second processor, wherein the BIST controller comprises:
an address generator configured to generate memory addresses for the cache of the second processor;
a data pattern generator configured to generate data patterns for storage into the cache;
control circuitry configured to store data generated by the data pattern generator at memory addresses of the cache generated by the address generator and to load data from the cache;
a data compare unit coupled to the control circuitry configured to determine if data values read from the cache match expected data values;
a random value generator coupled to the address generator; and
storage circuitry configured to store a random BIST enable (RBE) indicator, wherein, the first data processor is configured to assert the RBE indicator upon initiating execution of a secure code sequence, and the control circuitry is configured to, in response to assertion of the RBE indicator by the first processor, perform memory accesses to memory addresses of the cache generated by the address generator in response to the random value generator.
2. The data processing system of claim 1 , wherein the control circuitry is configured to continuously perform memory accesses to memory addresses of the cache generated by the address generator in response to the random value generator while the RBE indicator is asserted.
3. The data processing system of claim 2 , wherein the memory accesses are continuously performed to the memory addresses of the cache generated by the address generator in response to the random value generator at random time intervals while the RBE indicator is asserted, wherein the random time intervals are determined in response to the random value generator.
4. The data processing system of claim 2 , wherein the control circuitry is configured to stop performing memory accesses to memory addresses of the cache generated by the address generator in response to the random value generator in response to deassertion of the RBE indicator.
5. The data processing system of claim 4 , wherein the second processor is placed into an idle state prior to asserting the RBE indicator.
6. The data processing system of claim 5 , wherein the second processor is released from the idle state after deasserting the RBE indicator.
7. The data processing system of claim 1 , wherein when the RBE indicator is not asserted, the control circuitry is configured to:
store data patterns generated by the data pattern generator without using the random value generator to memory addresses of the cache generated by the address generator without using the random value generator,
read data values from the cache, and
provide the read data values from the cache to the data compare unit for comparison with the expected data values.
8. The data processing system of claim 1 , wherein the control circuitry is configured to store data patterns generated by the data pattern generator in response to the random value generator for at least a portion of the memory accesses performed to the memory addresses of the cache generated by the address generator in response to the random value generator.
9. In a data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the second processor which performs BIST memory accesses on the local memory of the second processor and stores a random BIST enable (RBE) indicator, a method comprising:
initiating, by the first processor, execution of a secure code sequence;
asserting the RBE indicator;
in response to assertion of the RBE indicator, initiating, by the BIST controller of the second processor, BIST memory accesses to the local memory of the second processor in response to a random value generator; and
executing, by the first processor, the secure code sequence concurrently with the BIST controller of the second processor performing BIST memory accesses to the local memory of the second processor in response to the random value generator.
10. The method of claim 9 , further comprising:
prior to asserting the RBE indicator, placing the second processor in an idle state.
11. The method of claim 10 , further comprising:
after executing the secure code sequence, deasserting the RBE indicator; and
in response to the deasserting the RBE indicator, the BIST controller of the second processor stopping the performing BIST memory accesses to the local memory of the second processor in response to the random value generator.
12. The method of claim 11 , further comprising:
after deasserting the RBE indicator, releasing the second processor from the idle state.
13. The method of claim 9 , wherein the performing the BIST memory accesses to the local memory of the second processor in response to the random value generator by the BIST controller comprises:
providing random values generated by the random value generator to an address generator of the BIST controller, wherein the address generator uses the random values to generate random addresses of the local memory for the BIST memory accesses.
14. The method of claim 13 , wherein each of the BIST memory accesses to the local memory is further characterized as a read access.
15. The method of claim 9 , wherein the performing the BIST memory accesses to the local memory of the second processor in response to the random value generator by the BIST controller comprises:
providing random values generated by the random value generator to a data pattern generator of the BIST controller, wherein the data pattern generator uses the random values to generate random data for storage in the local memory for the BIST memory accesses.
16. The method of claim 9 , wherein the performing the BIST memory accesses to the local memory of the second processor in response to the random value generator by the BIST controller comprises:
using random values generated by the random value generator to generate the BIST memory accesses at random time intervals.
17. The method of claim 9 , wherein when the RBE indicator is deasserted, the method further comprises:
performing BIST memory accesses to the local memory of the second processor by the BIST controller without using the random value generator;
reading, by the BIST controller, data values from the local memory; and
comparing, by the BIST controller, the read data values with expected data values.
18. The method of claim 9 , wherein the local memory of the second processor is further characterized as a cache of the second processor.
19. In a data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the second processor which performs BIST memory accesses on the local memory of the second processor and includes a random value generator, a method comprising: executing, by the first processor, a secure code sequence; and performing, by the BIST controller of the second processor, BIST memory accesses to the local memory of the second processor in response to the random value generator, wherein the performing the BIST memory accesses is performed concurrently with the executing the secure code sequence, wherein the performing the BIST memory accesses to the local memory of the second processor in response to the random value generator by the BIST controller comprises: using random values generated by the random value generator to generate at least one of random addresses of the local memory for the BIST memory accesses or random data for storage in the local memory for the BIST memory accesses.