IP Library Granted Patent US 8,435,874
Granted Patent B2
US 8,435,874 · App. 12/812,035 · Granted May 7, 2013

Method of forming openings in a semiconductor device and a semiconductor device fabricated by the method

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Quick Facts
Patent No.
US 8,435,874
App. No.
12/812,035
Granted
May 7, 2013
Kind
B2
Abstract

A method of forming openings to a layer of a semiconductor device comprises forming a dielectric layer over the layer of the semiconductor device, and forming a mask over the dielectric layer. The mask comprises a plurality of mask openings arranged in a regular pattern extending over the dielectric layer and the plurality of mask openings include a plurality of first mask openings and a plurality of second mask openings, each of the plurality of first mask openings being greater in size than each of the plurality of second mask openings. The method further comprises reducing the size of the plurality of second mask openings such that each of the second mask openings is substantially closed and removing portions of the dielectric layer through the plurality of first mask openings to provide openings extending through the dielectric layer to the layer.

Claims (31)

1. A method of forming openings to a layer of a semiconductor device comprising:

forming a dielectric layer over the layer of the semiconductor device;

forming a mask over the dielectric layer, the mask comprising a plurality of mask openings arranged in a pattern extending over the dielectric layer, the plurality of mask openings including a plurality of first mask openings and a plurality of second mask openings, each of the plurality of first mask openings being greater in size than each of the plurality of second mask openings;

reducing the size of the plurality of second mask openings such that each of the second mask openings is substantially closed, wherein reducing the size of the plurality of second mask openings comprises depositing a polymer over the mask and etching the deposited polymer and repeating the depositing and etching until the second mask openings are substantially closed; and

removing portions of the dielectric layer through the plurality of first mask openings to provide openings extending through the dielectric layer to the layer.

2. A method according to claim 1 , wherein forming a mask comprises:

providing a layout pattern for a layer of a semiconductor device including a plurality of first layout openings and a plurality of second layout openings arranged in a pattern, the size of the second layout openings being less than the size of the first layout openings;

forming a layer of photosensitive material over the dielectric layer; and

transferring the layout pattern to the layer of photosensitive material to form the mask over the dielectric layer, the first layout openings forming the first mask openings and the second layout openings forming the second mask openings.

3. A method according to claim 2 , wherein the providing a layout pattern comprises:

providing a layout pattern for a layer of a semiconductor device including the plurality of first layout openings; and

adding the plurality of second layout openings to the layout pattern such that the layout pattern includes the plurality of first and second layout openings arranged in a pattern.

4. A method according to claim 3 , wherein the providing and adding steps are performed by an OPC process.

5. A method according to claim 1 , wherein the first mask openings correspond to the openings to be formed to the layer.

6. A method according to claim 1 , wherein the pattern is a dense pattern.

7. A method according to claim 1 , wherein a pitch between adjacent first and second mask openings is substantially the same.

8. A method according to claim 1 , wherein the pattern of the plurality of mask openings is orientated with respect to an xy axes of a design layout for the semiconductor device such that a line through the centres of a line of the mask openings is at an angle A that is skewed relative to the x axis of the design layout.

9. A method according to claim 8 , wherein the angle A is 45° or is given by the following equation:

A =ArcTan( O. 5 /N )

where N is an integer (1, 2, 3, . . . ).

10. A method as claimed in claim 1 , further comprising forming an additional layer over the dielectric layer and wherein the openings are arranged to extend between the layer and the additional layer.

11. A method as claimed in any preceding claim 1 , wherein the openings are at least one of contact holes, vias, lines and trenches.

12. A method according to claim 2 , wherein the first mask openings correspond to the openings to be formed to the layer.

13. A method according to claim 3 , wherein the first mask openings correspond to the openings to be formed to the layer.

14. A method according to claim 2 , wherein the pattern is a dense pattern.

15. A method according to claim 3 , wherein the pattern is a dense pattern.

16. A method according to claim 2 , wherein a pitch between adjacent first and second mask openings is substantially the same.

17. A method according to claim 3 , wherein a pitch between adjacent first and second mask openings is substantially the same.

18. A method according to claim 1 , wherein the second mask openings have a size of substantially zero following reducing the size.

19. A method according to claim 1 , wherein, during removing portions of the dielectric layer, the dielectric layer is not removed through the substantially closed second mask openings.

20. A method according to claim 1 , wherein the pattern includes a grid pattern.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0285 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0334 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0387 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027621/0928 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0477 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0075 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 8, 2010
From: WARRICK, SCOTT; AMINPUR, MASSUD ABUBAKER; CONLEY, WILL; RIVIERE-CAZEAUX, LIONEL
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 024648/0383 →