Methods of making multi-state non-volatile memory cells
View Patent ↗A semiconductor device includes a region in a semiconductor substrate having a top surface with a first charge storage layer on the top surface. A first conductive line is on the first charge storage layer. A second charge storage layer is on the top surface. A second conductive line is on the second charge storage layer. A third charge storage layer is on the top surface. A third conductive line is on the third charge storage layer. A fourth charge storage layer has a first side adjoining a first sidewall of the first conductive line and a second side adjoining a first sidewall of the second conductive line. A fifth charge storage layer has a first side adjoining a second sidewall of the second conductive line and a second side adjoining a first sidewall of the third conductive line. Source and drain regions are formed in the substrate on either side of the semiconductor device.
1. A method of making a semiconductor device, comprising:
forming an isolation region surrounding an active region, wherein the active region is in a substrate;
depositing a first charge storage layer on a top surface of the active region and over the isolation region;
depositing a first layer comprising one of a group consisting of metal and polysilicon on the active region;
etching the first layer to leave a first line and a second line of the first layer across the active region and the isolation region;
after etching the first layer, depositing a second charge storage layer over the active region and the isolation region;
depositing a second layer comprising one of a group consisting of metal and polysilicon over the second charge storage layer;
removing portions of the second layer and the second charge storage layer to leave a third line between the first line and the second line and separated from the first line and the second line by a remaining portion of the second charge storage layer;
forming a drain on a first side of the first line, wherein the first side of the first line is away from the third line;
forming a source on a first side of the second line, wherein the first side of the second line is away from the third line; and
doping the first line, the second line, and the third line over the isolation region to a first conductivity type and doping the first line, the second line, and the third line over the active region to a second conductivity type.
2. The method of claim 1 , wherein:
the depositing the first layer is further characterized as depositing the first layer on the isolation region;
the etching the first layer leaves the first line and the second line on the isolation region;
the depositing the second charge storage layer deposits the second charge storage layer over the isolation region; and
the removing leaves the third line between the first and second lines and separated from the first and second lines by the second charge storage layer over the isolation region.
3. The method of claim 2 , wherein the depositing the first layer comprises depositing polysilicon and the depositing the second layer comprises depositing polysilicon.
4. The method of claim 1 , wherein:
the etching the first layer leaves a fourth line of the first layer across the active region; and
the removing portions of the second layer and the second charge storage layer leaves a fifth line between the second line and the fourth line separated from the second line and the fourth line by a second remaining portion of the second charge storage layer, wherein the removing portions comprises chemical mechanical polishing.
5. A method of making a semiconductor device, comprising:
forming an isolation region surrounding an active region, wherein the active region is in a substrate;
depositing a first charge storage layer on a top surface of the active region and on the isolation region;
depositing a first layer of polysilicon on the active region;
etching the first layer to leave a first line and a second line of the first layer across the active region and on the isolation region;
after etching the first layer, depositing a second charge storage layer over the active region and on the isolation region;
depositing a second layer of polysilicon over the second charge storage layer;
removing portions of the second layer and the second charge storage layer to leave a third line between the first line and the second line, wherein the third line remains across the active region and on the isolation region, and the third line is separated from the first line and the second line by a remaining portion of the second charge storage layer;
forming a drain on a first side of the first line, wherein the first side of the first line is away from the third line;
forming a source on a first side of the second line, wherein the first side of the second line is away from the third line; and
doping the first line, the second line, and the third line over the isolation region to p type and doping the first line, the second line, and the third line over the active region to n type.
6. The method of claim 5 , wherein:
the forming the isolation region further comprises surrounding a second active region;
the depositing the first charge storage layer further comprises depositing the first charge storage layer over the second active region;
the etching the first layer leaves the first line and the second line on the second active region;
the depositing the second charge storage layer deposits the second charge storage layer over the second active region; and
the removing leaves the third line between the first and second lines and separated from the first and second lines by the second charge storage layer over the second active region.
7. The method of claim 6 , the doping further comprises doping the first line, the second line, and the third line over the second active region to n type.
8. A method of forming a semiconductor device, comprising:
forming an isolation region around an active region of a substrate;
depositing a first charge storage layer comprising nanocrystals over the active region and the isolation region;
forming a first conductive line of polysilicon and a second conductive line of polysilicon across the active region and the isolation region and removing the first charge storage layer between the first and second conductive lines, wherein the first conductive line has a first sidewall facing a first sidewall of the second conductive line;
after forming the first conductive line and the second conductive line, depositing a second charge storage layer comprising nanocrystals over the active region and the isolation region;
forming a third conductive line of polysilicon over the second charge storage layer, the active region, and the isolation region, the third conductive line having a pair of sidewalls, wherein the third conductive line has a bottom surface on the second charge storage layer, the third conductive line is between the first and second conductive lines, and the second storage layer adjoins the pair of sidewalls of the third conductive line, the first sidewall of the first conductive line, and the first sidewall of the second conductive line; and
doping the first conductive line, the second conductive line, and the third conductive line over the isolation region to a first conductivity type and doping the first conductive line, the second conductive line, and the third conductive line over the active region to a different, second conductivity type.
9. The method of claim 8 , wherein:
the forming the isolation region further comprises surrounding a second active region;
the depositing the first charge storage layer further comprises depositing the first charge storage layer over the second active region;
the forming the first conductive line and the second conductive line comprises forming the first conductive line and the second conductive line over the second active region;
the depositing the second charge storage layer deposits the second charge storage layer over the second active region; and
the forming the third conductive line comprises forming the third conductive line on the second charge storage layer over the second active region.
10. The method of claim 9 , the doping further comprises doping the first conductive line, the second conductive line, and the third conductive line over the second active region to the second conductivity type.