Selective routing of local memory accesses and device thereof
View Patent ↗A data processor is disclosed that accesses its local memory by routing requests through a data path that is external the data processor. A reservation/decoration controller implements specialized handling associated with a received request to access local memory. In addition to implementing special handling, a memory controller that is associated with the reservation/decoration controller routes a corresponding access request back to the data processor core to access its local memory.
1. A method comprising:
determining that an access instruction being executed at a data processor core is or is not a specialized access instruction; and
selectively routing access information based on the access instruction to access a local memory of the data processor core using a transaction external the data processor core responsive to determining that the access instruction is the specialized access instruction, wherein the specialized access instruction is at least one of an atomic access instruction or a decorated access instruction.
2. The method of claim 1 further comprising:
selectively routing the access information to access the local memory of the data processor core using a transaction internal the data processor core responsive to determining that the access instruction is not the specialized access instruction.
3. The method of claim 2 , wherein the determining is based upon information embedded in the access instruction.
4. The method of claim 2 , wherein the determining based upon register information.
5. The method of claim 2 , wherein using the transaction external the data processor core includes routing the access information from a port of the data processor core to a system resource external the data processor core, and the system resource used to route the access information to the data processor core to access the local memory.
6. The method of claim 5 further comprising: responsive to selectively routing the access information to the local memory, receiving at the system resource, from the local memory, data being accessed based on the access information.
7. The method of claim 2 , wherein using the transaction external the data processor core includes routing the access information from a first port of the data processor core to a system resource external the data processor core that is used to route the access information to the data processor core via a second port of the data processor core to access the local memory.
8. The method of claim 5 further comprising: ensuring, at the system resource, that a memory associated with the access information is atomically accessed in response to the access instruction being an atomic access instruction.
9. The method of claim 5 further comprising: manipulating, at the system resource, access information to be stored at the local memory in response to the access instruction being a decorated access instruction.
10. The method of claim 1 further comprising determining whether a programmable indicator is in a first state that indicates that use of the transaction external the data processor core is enabled, or in a second state that indicates that use of the transaction external the data processor core is not enabled, and in response to determining that the programmable indicator is enabled implementing the selectively routing using the transaction external the data processor core, and in response to determining that the programmable indicator is not enabled selectively routing the access information from the specialized access instruction to the local memory without using any transaction external the data processor core responsive.
11. The method of claim 1 , wherein the specialized access instruction is an atomic instruction.
12. The method of claim 1 , wherein the specialized access instruction is a decorated access instruction.
13. A device comprising:
a plurality of data processor cores including a first data processor core comprising a first local memory;
a system resource module external the data processor core;
a system interconnect coupled to the system resource module and to the first data processor core; and
the first data processor core to selectively route access information associated with an access instruction being executed at an instruction processor pipeline of the first data processor core to the system resource module responsive to the access instruction being a specialized access instruction that includes at least one of an atomic access instruction or a decorated access instruction.
14. The device of claim 13 , wherein the system resource module is to further route the access information to the first data processor core to access the first local memory in response to the access instruction being identified as the specialized access instruction.
15. The device of claim 13 , wherein the instruction processor pipeline is to determine whether the access instruction is the specialized access instruction or not the specialized access instruction, the instruction processing pipeline to further, in response to determining the access instruction is not the specialized access instruction, to selectively route the access information associated with the access instruction to the local memory without using the system resource module, to allow the first local memory to be accessed local to the first data processor core.
16. The first data processor core of claim 13 further comprising a first port coupled the system interconnect and a second port coupled to the system interconnect, the first data processor core to selectively route the access information to the system resource module via the first port responsive to the access instruction being identified as the specialized access instruction, and the system resource module to provide the access information to the first local memory via the second port of the data processor.
17. The device of claim 13 , wherein the plurality of data processor cores further includes a second data processor core coupled to the system interconnect, the second data processor core comprising a second local memory; and
the second data processor core to selectively route access information associated with an access instruction being executed at an instruction processor pipeline of the second data processor core to the system resource module, responsive to the second access instruction being identified as the specialized access instruction, wherein the system resource module is to further route the access information associated with the second data processor core to the second data processor core to access the second local memory.
18. The device of claim 17 , wherein the system resource module is a memory controller that is to manipulates information being stored or retrieved.
19. The device of claim 13 further comprising a storage location to store an enable indicator, wherein the first data processor core further selectively routes the access information to the system resource responsive to the enable indicator being asserted, and selectively routes the access information to the local memory without using the system resource responsive to the enable indicator being negated.
20. A method comprising:
determining whether a first access request being executed at a first data processor core is an atomic access request to access a local memory of the first data processor core;
in response to determining the first access request is the atomic access request, ensuring the first access request is implemented in an atomic manner using a resource external the first data processor core to access the local memory of the first data processor core, otherwise, in response to determining the first access request is not the atomic access request, accessing the local memory of the first data processor core without using any resources external the data processor core;
determining whether a second access request being executed at a second data processor core is an atomic access request to access a local memory of the second data processor core;
in response to determining the second access request is an atomic access request, ensuring the second access request is implemented in the atomic manner using the resource external the first data processor core to access the local memory of the second data processor core, wherein the resource is also external the second data processor core; and
in response to determining the second access request is not the atomic access request, accessing the local memory of the second processor core without using any resources external the second data processor core.