LDO linear regulator with improved transient response
View Patent ↗An LDO regulator system has first and second current mirror circuits connected to its output terminal. A load attached to the output terminal is supplied with a constant voltage. Variations in the load that cause variations in the magnitude of the output voltage trigger one of the first or second current mirror circuits to generate a current that varies the magnitude of a gate voltage of a pass-transistor. The variation in the gate voltage in turns varies the drain current of the pass-transistor, which varies the output voltage to counter the change in the magnitude of the output voltage. Using the first and second current mirror circuits avoids the need for a large load capacitor and very high bandwidth of a conventional LDO regulator.
1. A voltage regulating system that receives an external reference voltage and generates an output voltage, the system comprising:
a low dropout (LDO) regulator that includes:
an error amplifier for comparing the external reference voltage and a scaled-down version of the output voltage to generate an error amplified signal; and
a pass transistor having a gate connected to the error amplifier, a source connected to a voltage source, and a drain connected to a load, wherein the pass transistor generates the output voltage based on the error amplified signal;
a transient response circuit, connected to the LDO regulator, for improving a transient response of the LDO regulator, the transient response circuit including:
a first current mirror connected to the pass transistor, wherein an input terminal of the first current mirror is connected to the drain of the pass transistor and an output terminal of the first current mirror is connected to the gate of the pass transistor; and
a second current mirror connected to the pass-transistor, wherein an input terminal of the second current mirror is connected to the drain of the pass transistor and an output terminal of the second current mirror is connected to the gate of the pass transistor.
2. The system of claim 1 , wherein the first current mirror comprises:
a first capacitor connected to the input terminal of the first current mirror;
a first PMOS transistor having a source terminal connected to the voltage source, and a gate terminal connected to the input terminal of first current mirror by way of the first capacitor and to a drain terminal of the first PMOS transistor;
a second PMOS transistor having a source terminal connected to the voltage source and a gate terminal connected to the gate of the first PMOS transistor;
a first current source connected between the drain terminal of the first PMOS transistor and ground;
a first NMOS transistor having a drain terminal connected to the output terminal of the first current mirror, and a drain terminal connected to the ground; and
a second NMOS transistor having a gate terminal connected to the gate terminal of the first NMOS transistor and the drain of the second PMOS transistor, a source terminal connected to the ground, and a drain terminal connected to the drain terminal of the second PMOS transistor.
3. The system of claim 2 , wherein the first PMOS transistor and the first current source act as a biasing circuit for the second PMOS transistor, wherein during steady-state operation the second PMOS transistor operates in the saturation region and is kept in the saturation region by the biasing circuit.
4. The system of claim 2 , wherein the second current mirror comprises:
a second capacitor connected to the input terminal of the second current mirror;
a third NMOS transistor having a gate terminal connected to the input terminal of the second current mirror by way of the second capacitor, and a source terminal connected to ground;
a fourth NMOS transistor having a gate terminal connected to the gate terminal of the third NMOS transistor, a source terminal connected to the ground, and a drain terminal connected to its gate terminal;
a second current source connected between the voltage source and the drain terminal of the fourth NMOS transistor;
a third PMOS transistor having a source terminal connected to the voltage source, and a drain terminal connected to the output terminal of the second current mirror; and
a fourth PMOS transistor having a source terminal connected to the voltage source, a drain terminal connected to a drain terminal of the third NMOS transistor, and a gate connected to its drain terminal and to the gate terminal of the third PMOS transistor.
5. The system of claim 4 , wherein the fourth NMOS transistor and the second current source act as a second biasing circuit for the third NMOS transistor, wherein during steady-state operation the third NMOS transistor operates in the saturation region and is kept in the saturation region by the second biasing circuit.