Granted Patent B2

US 8,489,906 · App. 12/786,916 · Granted Jul 16, 2013

Abstract

Claims (56)

1. A processor comprising:

a first virtual ground terminal;

a second virtual ground terminal;

circuitry coupled to the first virtual ground terminal for providing current to the first virtual ground terminal;

a first regulating transistor coupled between the first virtual ground terminal and the second virtual ground terminal;

a first disabling transistor coupled in parallel with the first regulating transistor for selectively disabling the first regulating transistor by directly connecting the second virtual ground terminal to the first virtual ground terminal;

a second regulating transistor coupled between the second virtual ground terminal and a first ground terminal; and

a second disabling transistor coupled in parallel with the second regulating transistor for selectively disabling the second regulating transistor by directly connecting the second virtual ground terminal to the first ground terminal.

2. The processor of claim 1 , further comprising:

a first bias circuit coupled between a power supply voltage terminal and the second virtual ground terminal and having an input coupled to the first virtual ground terminal and having an output coupled to a control electrode of the first regulating transistor; and

a second bias circuit coupled between the power supply voltage terminal and the first ground terminal and having an input coupled to the second virtual ground terminal and having an output coupled to a control electrode of the second regulating transistor.

3. The processor of claim 1 , wherein the current provided by the circuitry to the first node is a leakage current which occurs during a lower power mode.

4. The processor of claim 1 , wherein the circuitry is coupled to a power supply voltage terminal, wherein a voltage at the first virtual ground terminal is less than a voltage at the power supply voltage terminal and greater than ground.

5. The processor of claim 4 , wherein a voltage at the first virtual ground terminal is less than a voltage at the power supply voltage terminal and greater than the voltage at the second virtual ground terminal.

6. The processor of claim 1 , wherein the circuitry comprises a memory, and wherein only one of the first regulating transistor and the second regulating transistor is enabled during a lower power mode such that loss of state in the memory is prevented.

7. The processor of claim 1 , wherein the circuitry comprises a functional block which performs a processor operation, and wherein one or more of the first regulating transistor and the second regulating transistor is enabled during a low power mode.

8. The processor of claim 7 , wherein, upon exiting the low power mode, the second regulating transistor is disabled prior to disabling the first regulating transistor.

9. A processor comprising:

a first virtual terminal;

a second virtual terminal;

a first power supply terminal;

a second power supply terminal;

circuitry coupled between the second power supply terminal and the first virtual terminal;

a first voltage regulator coupled between the first virtual terminal and the second virtual terminal;

a second voltage regulator coupled between the second virtual terminal and the first power supply terminal, wherein:

when the first voltage regulator is enabled, a voltage between the second power supply terminal and the first virtual terminal is less than a voltage between the second power supply terminal and the second virtual terminal, and

when the second voltage regulator is enabled, a voltage between the second power supply terminal and the second virtual terminal is less than a voltage between the second power supply terminal and the first power supply terminal.

10. The processor of claim 9 , wherein:

when the first voltage regulator is disabled, a voltage between the second power supply terminal and the first virtual terminal is substantially the same as a voltage between the second power supply terminal and the second virtual terminal, and

when the second voltage regulator is disabled, a voltage between the second power supply terminal and the second virtual terminal is substantially the same as a voltage between the second power supply terminal and the first power supply terminal.

11. The processor of claim 9 , wherein the first power supply voltage terminal is a ground reference terminal.

12. The processor of claim 9 , wherein the circuitry comprises a memory, and wherein, during a low power mode, only one of the first voltage regulator and the second voltage regulator is enabled to prevent loss of state of the memory.

13. The processor of claim 9 , wherein the circuitry comprises a functional block which performs a processor operation, and wherein, during a low power mode, one or more of the first voltage regulator and the second voltage regulator is enabled.

14. The processor of claim 13 , wherein during a deep low power mode, both the first voltage regulator and the second voltage regulator are enabled.

15. The processor of claim 14 , wherein, upon exiting the deep low power mode, the second voltage regulator is disabled prior to disabling the first voltage regulator.

16. A processor comprising:

a first virtual power supply terminal;

a second virtual power supply terminal;

a third virtual power supply terminal;

a first power supply terminal;

a second power supply terminal;

functional circuitry which performs a processor operation coupled between the second power supply terminal and the first virtual power supply terminal;

a first voltage regulator coupled between the first virtual power supply terminal and the second virtual power supply terminal;

a memory coupled between the second power supply terminal and the third virtual power supply terminal;

a second voltage regulator coupled between the third virtual power supply terminal and the second virtual power supply terminal; and

a third voltage regulator coupled between the second virtual power supply terminal and the first power supply terminal, wherein:

when the first voltage regulator is enabled, a voltage between the second power supply terminal and the first virtual power supply terminal is less than a voltage between the second power supply terminal and the second virtual power supply terminal,

when the second voltage regulator is enabled, a voltage between the second power supply terminal and the third virtual power supply terminal is less than a voltage between the second power supply terminal and the second virtual power supply terminal, and

when the third voltage regulator is enabled, a voltage between the second power supply terminal and the second virtual power supply terminal is less than a voltage between the second power supply terminal and the first power supply terminal.

17. The processor of claim 16 , wherein:

when the first voltage regulator is disabled, the first virtual power supply terminal is directly connected to the second virtual power supply terminal,

when the second voltage regulator is disabled, the third virtual power supply terminal is directly connected to the second virtual power supply terminal, and

when the third voltage regulator is disabled, the second virtual power supply terminal is directly connected to the second power supply terminal.

18. The processor of claim 17 , wherein, during a low power mode, only one of the second voltage regulator and the third voltage regulator is enabled to prevent loss of state of the memory.

19. The processor of claim 17 , wherein, during a deep low power mode, both the first voltage regulator and the second voltage regulator are enabled.

20. The processor of claim 19 , wherein, upon exiting the deep low power mode, the third voltage regulator is disabled prior to disabling the second voltage regulator.

Assignments (22)