Non-volatile memory (NVM) cell for endurance and method of making
View Patent ↗A first dielectric is formed over a semiconductor layer, a first gate layer over the first dielectric, a second dielectric over the first gate layer, and a third dielectric over the second dielectric. An etch is performed to form a first sidewall of the first gate layer. A second etch is performed to remove portions of the first dielectric between the semiconductor layer and the first gate layer to expose a bottom corner of the first gate layer and to remove portions of the second dielectric between the first gate layer and the third dielectric layer to expose a top corner of the first gate layer. An oxide is grown on the first sidewall and around the top and bottom corners to round the corners. The oxide is then removed. A charge storage layer and second gate layer is formed over the third dielectric layer and overlapping the first sidewall.
1. A method for forming a semiconductor device comprising:
forming a first dielectric layer over a semiconductor layer;
forming a first conductive gate layer over the first dielectric layer;
forming a second dielectric layer over the first conductive gate layer;
forming a third dielectric layer over the second dielectric layer, the third dielectric layer having a different etch characteristic than the second dielectric layer;
performing a first etch to form a first sidewall of the first conductive gate layer, wherein the first etch exposes a portion of the semiconductor layer;
performing a second etch to remove a portion of the first dielectric layer between the semiconductor layer and the first conductive gate layer, resulting in a first undercut between the semiconductor layer and the first conductive gate layer, and to remove a portion of the second dielectric layer between the third dielectric layer and the first conductive gate layer, resulting in a second undercut between the third dielectric layer and the first conductive gate layer, wherein the first undercut exposes a bottom corner of the first conductive gate layer and the second undercut exposes a top corner of the first conductive gate layer;
growing an oxide layer on the first sidewall of the first conductive gate layer, around the top corner and around the bottom corner of the first conductive gate layer, and over the exposed portion of the semiconductor layer, wherein the growing the oxide layer results in rounding each of the top corner and the bottom corner of the first conductive gate layer;
removing the oxide layer;
forming a charge storage layer over the third dielectric layer, along the first sidewall of the first conductive gate layer, and over the semiconductor layer;
forming a second conductive gate layer over the charge storage layer; and
patterning the second conductive gate layer to form a first sidewall of the second conductive gate layer over the first conductive gate layer and a second sidewall of the second conductive gate layer over the semiconductor layer, wherein the second conductive gate layer overlaps the first sidewall of the first conductive gate layer and overlaps a top portion of the first conductive gate layer.
2. The method of claim 1 , wherein the step of patterning the second conductive gate layer comprises:
patterning the first conductive gate layer to form a second sidewall of the first conductive gate layer.
3. The method of claim 1 , wherein after the step of patterning the second conductive gate layer, the method further comprises:
removing an exposed portion of the third dielectric layer that is exposed by the second conductive gate layer such that a remaining portion of the third dielectric layer remains between second conductive gate layer and the top portion of the first conductive gate layer that is overlapped by the second conductive gate layer.
4. The method of claim 1 , wherein the step of forming the third dielectric layer over the second dielectric layer is further characterized in that the third dielectric layer is an anti-reflective coating (ARC) layer.
5. The method of claim 1 , wherein the step of forming the second dielectric over the first conductive gate layer comprises growing the second dielectric layer in an ozone environment.
6. The method of claim 1 , wherein the step of performing the first etch to form the first sidewall of the first conductive gate layer also forms a second sidewall of the first conductive gate layer.
7. The method of claim 1 , wherein the step of forming the charge storage layer comprises:
forming a bottom oxide layer;
forming a plurality of nanocrystals over the bottom oxide layer; and
forming a top oxide layer over and surrounding the plurality of nanocrystals.
8. The method of claim 1 , wherein the first conductive gate layer is further characterized as a select gate layer and the second conductive gate layer is further characterized as a control gate layer.
9. The method of claim 8 , further comprising:
forming sidewall spacers adjacent a second sidewall of the first conductive gate layer, the first sidewall of the second conductive gate layer, and the second sidewall of the second conductive gate layer;
forming a first source/drain region in the semiconductor layer laterally adjacent the second sidewall of the first conductive gate layer; and
forming a second source/drain region in the semiconductor layer laterally adjacent the second sidewall of the second conductive gate layer.
10. The method of claim 1 , wherein each of the first and second conductive gate layers comprise polysilicon.
11. A method for forming a semiconductor device comprising:
forming a gate dielectric layer over a semiconductor layer;
forming a select gate layer over the gate dielectric layer, wherein the select gate layer comprises polysilicon;
forming a first dielectric layer over the select gate layer;
forming an anti-reflective coating (ARC) layer over the first dielectric layer;
performing a first etch to form a select gate portion from the select gate layer having a first sidewall, wherein the first etch exposes a portion of the semiconductor layer;
performing a second etch to remove a portion of the gate dielectric layer between the semiconductor layer and the select gate layer, such that the gate dielectric layer under the select gate layer is recessed from the first sidewall of the select gate portion to expose a bottom corner of the select gate layer, and to remove a portion of the first dielectric layer between the ARC layer and the select gate portion, such that the first dielectric layer over the select gate portion is recessed from the first sidewall of the select gate portion to expose a top corner of the select gate portion;
growing an oxide layer on the first sidewall of the select gate portion, around the top corner and around the bottom corner of the first conductive gate layer, and over the exposed portion of the semiconductor layer, wherein the growing the oxide layer results in rounding each of the top corner and the bottom corner of the select gate portion;
removing the oxide layer;
forming a charge storage layer over the select gate portion, along the first sidewall of the select gate portion, and over the semiconductor layer;
forming a control gate layer over the charge storage layer, wherein the control gate layer comprises polysilicon; and
patterning the control gate layer to form a first sidewall of the control gate layer over the select gate portion and a second sidewall of the control gate layer over the semiconductor layer, wherein the control gate layer overlaps the first sidewall of the select gate portion and overlaps a top portion of the select gate portion.
12. The method of claim 11 , wherein after the step of patterning the control layer, the method further comprises:
removing an exposed portion of the ARC layer that is exposed by the control gate layer such that a remaining portion of the ARC layer remains between the control gate layer and the top portion of the select gate layer that is overlapped by the control gate layer.
13. The method of claim 11 , wherein the step of forming the first dielectric over the select gate layer comprises growing the first dielectric layer in an ozone environment.
14. The method of claim 11 , wherein the step of forming the charge storage layer comprises:
forming a bottom oxide layer;
forming a plurality of nanocrystals over the bottom oxide layer; and
forming a top oxide layer over and surrounding the plurality of nanocrystals.
15. The method of claim 11 , further comprising:
forming sidewall spacers adjacent a second sidewall of the select gate portion, the first sidewall of the control gate layer, and the second sidewall of the control gate layer;
forming a first source/drain region in the semiconductor layer laterally adjacent the second sidewall of the select gate layer; and
forming a second source/drain region in the semiconductor layer laterally adjacent the second sidewall of the control gate layer.
16. The method of claim 11 , wherein the step of patterning the control gate layer comprises:
patterning the select gate layer to form a second sidewall of the select gate layer.
17. The method of claim 11 , wherein the step of performing the first etch to form the first sidewall of the select gate layer also forms a second sidewall of the select gate layer.
18. A split gate memory cell comprising:
a semiconductor substrate;
a gate dielectric over the semiconductor substrate;
a select gate over the gate dielectric, wherein the select gate has a sidewall, and wherein a top corner of the select gate at the sidewall is rounded and a bottom corner of the select gate at the sidewall is rounded;
a charge storage layer comprising a plurality of nanocrystals over the semiconductor substrate and overlapping the sidewall of the select gate including along the rounded to corner and the rounded bottom corner, wherein a portion of the charge storage layer overlaps a portion of the select gate; and
a control gate over the charge storage layer, wherein the control gate overlaps the sidewall of the select gate and overlaps the portion of the select gate, wherein the control gate has a sidewall over the select gate and the charge storage layer is between the select gate and the control gate where sidewall of the control gate overlaps the portion of the select gate and where the sidewall of the control gate is over the select gate.
19. The split gate memory cell of claim 18 , further comprising:
a first dielectric over the portion of the select gate overlapped by the charge storage layer and under the charge storage layer such that the first dielectric is between the select gate and the charge storage layer and extends to a sidewall spacer located adjacent the sidewall of the control gate.
20. The split gate memory cell of claim 19 , further comprising:
an anti-reflective coating (ARC) layer over the first dielectric over the portion of the select gate overlapped by the charge storage layer and under the charge storage layer such that the ARC layer is between the first dielectric and the charge storage layer and extends to the sidewall spacer located adjacent the sidewall of the control gate.