Methods of forming semiconductor devices having conductors with different dimensions
View Patent ↗A device structure includes an inter-level dielectric, a via, a first conductive trench, and a second conductive trench. The inter-level dielectric has a top surface and a bottom surface. The via extends from the top surface to the bottom surface. The first conductive trench extends from the top surface to a first depth below the top surface. The second conductive trench extends from the top surface to a second depth below the top surface, wherein the second depth is above the bottom surface and below the first depth.
1. A method of making a device structure in an inter-level dielectric having a top surface and a bottom surface, comprising:
etching a first opening through the inter-level dielectric;
etching a first trench partially through the inter-level dielectric to a first depth, wherein the first trench has a first width;
forming a patterned photoresist layer on the inter-level dielectric to protect the first trench from further etching;
after forming the patterned photoresist layer, etching the inter-level dielectric through an opening in the patterned photoresist layer to form a second trench that extends partially through the inter-level dielectric to a second depth deeper than the first depth, wherein the second trench has a second width that is wider than the first width;
removing the patterned photoresist layer; and
filling the first opening, the first trench, and the second trench with conductive material.
2. The method of claim 1 , further comprising:
etching a third trench adjacent to the second trench partially through the inter-level dielectric to the second depth; and
filling the third trench with conductive material.
3. The method of claim 2 , wherein etching the third trench occurs while etching the second trench and filling the third trench occurs while filing the first opening, the first trench, and the second trench.
4. A method of making a device structure in an inter-level dielectric having a top surface and a bottom surface, comprising:
etching a first opening through the inter-level dielectric;
etching a first trench partially through the inter-level dielectric to a first depth;
etching a second trench opening partially through the inter-level dielectric to a first width at the top surface and to a second depth deeper than the first depth;
etching a third trench partially through the inter-level dielectric to the second depth wherein the third trench has a second width greater than the first width at the top surface; and
filling the first opening, the first trench, the second trench, and the third trench with conductive material.
5. The method of claim 4 , wherein etching the third trench occurs while etching the second trench and filling the third trench while filing the first opening, the first trench, and the second trench.
6. The method of claim 4 , wherein the third trench is filled with conductive material functions as a power supply line.
7. The method of claim 4 , further comprising:
etching a fourth trench adjacent to the second trench partially through the inter-level dielectric to the second depth; and
filling the fourth trench with conductive material to form a fringe capacitor with the second trench filled with conductive material.
8. The method of claim 4 , wherein the step of filling is further characterized as filling with copper.
9. A method of forming a device structure including a fringe capacitor, comprising:
forming a via opening through an inter-level dielectric;
forming a first trench through the inter-level dielectric to a first depth;
forming a patterned photoresist layer to protect the first trench;
after forming the patterned photoresist layer, forming a plurality of capacitor electrode trenches adjacent to each other by etching the inter-level dielectric through a plurality of openings in the patterned photoresist layer to a second depth greater than the first depth, wherein the plurality of capacitor electrode trenches each has a first width;
forming a second trench having a second width greater than the first width formed while forming the pair of capacitor electrode trenches;
removing the patterned photoresist layer; and
filling the via opening, the first trench, the second trench, and the plurality of capacitor electrode trenches with conductive material, wherein filling the plurality of capacitor electrode trenches forms the fringe capacitor, and filling the second trench forms a power line in the second trench.
10. The method of claim 9 , wherein the step of filling comprises filling with copper.
11. A method of forming a semiconductor device, the method comprising:
providing an inter-level dielectric having a top surface and a bottom surface;
forming a via extending from the top surface to the bottom surface;
forming a first conductive trench having a first width and extending from the top surface to a first depth below the top surface by etching a first trench in the inter-level dielectric to the first depth, and filling the first trench with conductive material; and
forming a second conductive trench having a second width that is wider than the first width and extending from the top surface to a second depth below the top surface, wherein the second depth is above the bottom surface and below the first depth, and wherein the second conductive trench is formed by applying a patterned photoresist layer on a surface of the inter-level dielectric to protect the first trench, etching through an opening in the patterned photoresist layer to form a second trench to the second depth, and filling the second trench with the conductive material.
12. The method of claim 11 , further comprising:
forming a third conductive trench extending from the top surface to the second depth below the top surface and adjacent to the second conductive trench.
13. A method of forming a semiconductor device, the method comprising:
providing an inter-level dielectric having a top surface and a bottom surface;
forming a via extending from the top surface to the bottom surface;
forming a first conductive trench extending from the top surface to a first depth below the top surface, wherein the first conductive trench has a first width at the top surface;
forming a second conductive trench extending from the top surface to a second depth below the top surface, wherein the second depth is above the bottom surface and below the first depth; and
forming a third conductive trench extending to the second depth and having a second width at the top surface, wherein the second width is greater than the first width.
14. The method of claim 13 , wherein the third conductive trench is a power supply line.
15. The method of claim 14 , further comprising:
forming a fourth conductive trench extending from the top surface to the second depth below the top surface and adjacent to the second conductive trench to form a fringe capacitor between the second conductive trench and the fourth conductive trench.
16. The method of claim 13 , wherein the first conductive trench and the second conductive trench comprise copper.
17. The method of claim 16 , further comprising:
forming a cap layer on the bottom surface.
18. The method of claim 17 , further comprising:
forming a second inter-level dielectric layer adjoining the cap layer.