Circuit having gate drivers having a level shifter
View Patent ↗A circuit comprises a first level shifting circuit. The level shifting circuit comprises a first and second latching differential pairs. The first latching differential pair has first and second inputs for receiving first and second input signals, first and second outputs, and first and second power supply voltage terminals for receiving a first power supply voltage. The second latching differential pair has first and second inputs coupled to the first and second outputs of the first latching differential pair, an output, and first and second power supply voltage terminals for receiving a second power supply voltage, the second power supply voltage being different from the first power supply voltage. In one embodiment, the level shifting circuit protects transistor gates of the circuit from an overvoltage.
1. A circuit comprising:
a first level shifting circuit comprising:
a first latching differential pair having first and second inputs for receiving first and second input signals, first and second outputs, and first and second power supply voltage terminals for receiving a first power supply voltage;
a second latching differential pair having first and second inputs coupled to the first and second outputs of the first latching differential pair, an output, and first and second power supply voltage terminals for receiving a second power supply voltage, the second power supply voltage being different from the first power supply voltage;
a first plurality of delay elements coupled in series and having an input coupled to the output of the second latching differential pair, and an output;
a first gate driver circuit having an input coupled to the output of the first plurality of delay elements; and an output; and
a first drive transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode coupled to the output of the first gate driver circuit, and a second current electrode coupled to an output terminal of the circuit.
2. The circuit of claim 1 , wherein the first power supply voltage terminal of the first latching differential pair is coupled to a first voltage level, the second power supply voltage terminal of the first latching differential pair is coupled to ground, the first power supply voltage terminal of the second latching differential pair is coupled to the first voltage level, and the second power supply voltage terminal of the second latching differential pair coupled to a second voltage level, wherein the second voltage level is between the first voltage level and ground.
3. The circuit of claim 1 , further comprising:
a first logic gate having an output coupled to one of the first and second inputs of the first latching differential pair, and first and second power supply voltage terminals for receiving a third power supply voltage different from the first power supply voltage and the second power supply voltage.
4. The circuit of claim 1 , further comprising:
a second level shifting circuit having an input for receiving an input signal at a first voltage level, and an output for providing an output signal at a second voltage level;
a second plurality of delay elements coupled in series and having an input coupled to the output of the second level shifting circuit, and an output;
a second gate driver circuit having an input coupled to the output of the second plurality of delay elements, and an output; and
a second drive transistor having a first current electrode coupled to the second current electrode of the first drive transistor, a control electrode coupled to the output of the output of the second gate driver circuit, and a second current electrode coupled to ground.
5. The circuit of claim 4 , further comprising:
a third level shifting circuit having an input coupled to the output of the first gate driver circuit, and an output coupled to the input of the second level shifting circuit; and
a fourth level shifting circuit having an input coupled to the output of the second gate driver circuit, and an output coupled to the input of the first level shifting circuit.
6. The circuit of claim 5 , wherein the first, second, third, and fourth level shifting circuits each provide substantially a same gate delay.
7. The circuit of claim 1 , wherein the first latching differential pair comprises:
a first transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode, and a second current electrode;
a second transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode coupled to the second current electrode of the first transistor, and a second current electrode coupled to the control electrode of the first transistor;
a third transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode for receiving the first input signal, and a second current electrode coupled to the second power supply voltage terminal; and
a fourth transistor having a first current electrode coupled to the second current electrode of the second transistor, a control electrode for receiving the second input signal, and a second current electrode coupled to the second power supply voltage terminal.
8. The circuit of claim 1 , wherein the first power supply voltage is higher than the second power supply voltage.
9. A circuit comprising:
a first level shifter circuit comprising:
a first transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode, and a second current electrode;
a second transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode coupled to the second current electrode of the first transistor, and a second current electrode coupled to the control electrode of the first transistor;
a third transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode for receiving a first input signal, and a second current electrode coupled to a second power supply voltage terminal;
a fourth transistor having a first current electrode coupled to the second current electrode of the second transistor, a control electrode for receiving a second input signal, and a second current electrode coupled to the second power supply voltage terminal;
a fifth transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode, and a second current electrode;
a sixth transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode coupled to the second current electrode of the fifth transistor, and a second current electrode coupled to the control electrode of the fifth transistor at a first output terminal;
a seventh transistor having a first current electrode coupled to the second current electrode of the fifth transistor, a control electrode coupled to the first current electrode of the third transistor, and a second current electrode coupled to a third power supply voltage terminal;
an eighth transistor having a first current electrode coupled to the second current electrode of the sixth transistor, a control electrode coupled to the first current electrode of the fourth transistor, and a second current electrode coupled to the third power supply voltage terminal;
a first delay circuit having an input coupled to the first output terminal, and an output;
a first driver circuit having an input coupled to the output of the first delay circuit, and an output; and
a first drive transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode coupled to the output of the first driver circuit, and a second current electrode coupled to an output terminal of the circuit.
10. The circuit of claim 9 , wherein the third power supply voltage is greater than the second power supply voltage and less than the first power supply voltage.
11. A circuit comprising:
a first level shifting circuit comprising:
a first latching differential pair having first and second inputs for receiving first and second input signals, first and second outputs, and first and second power supply voltage terminals for receiving a first power supply voltage; and
a second latching differential pair having first and second inputs coupled to the first and second outputs, respectively, of the first latching differential pair, an output, and first and second power supply voltage terminals for receiving a second power supply voltage, the second power supply voltage being different from the first power supply voltage;
a first delay circuit having an input coupled to the output of the second latching differential pair, and an output;
a first driver circuit having an input coupled to the output of the first delay circuit, and an output; and
a first drive transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode coupled to the output of the first driver circuit, and a second current electrode coupled to an output terminal of the circuit.