Methods and apparatus for orthogonal modulated signals
View Patent ↗Methods and corresponding systems for providing and demodulating an orthogonal modulated signal where demodulation includes separating a sampled orthogonal modulated signal into in phase and quadrature samples, deriving first and second equalizer coefficients based on corresponding in phase and quadrature samples and further, respectively, based on a first and second training sequence, programming a first plurality of equalizer filters with the first equalizer coefficients and a second plurality of equalizer filters with the second equalizer coefficients; and processing, after programming with first and second coefficients, the in phase samples and the quadrature samples through a first and second plurality of equalizer filters to provide demodulated symbols.
1. A method of demodulating an orthogonal modulated signal, the method comprising:
separating a sampled signal including a training portion and an information portion into in phase samples and quadrature samples, the sampled signal corresponding to the orthogonal modulated signal;
deriving first equalizer coefficients and second equalizer coefficients based on the training portion and corresponding in phase samples and corresponding quadrature samples and further, respectively, based on a first training sequence and on a second training sequence;
programming a first plurality of equalizer filters with the first equalizer coefficients and a second plurality of equalizer filters with the second equalizer coefficients; and
processing, after the programming, the in phase samples and the quadrature samples from the information portion through the first and second plurality of equalizer filters to provide demodulated symbols.
2. The method of claim 1 wherein the sampled signal is first de-rotated on a sample by sample basis prior to the separating into in phase and quadrature samples.
3. The method of claim 1 wherein the deriving first equalizer coefficients further comprises performing a first Minimum Square Error (MSE) solution to a convolution of the in phase and the quadrature samples and respective sets of the first equalizer coefficients less the first training sequence.
4. The method of claim 3 wherein the deriving first equalizer coefficients further comprises, performing the first MSE solution at a plurality of time trials and evaluating a performance metric to select a time reference for the first plurality of equalizer filters.
5. The method of claim 3 wherein the deriving second equalizer coefficients further comprises performing a second Minimum Square Error (MSE) solution to a convolution of the in phase and the quadrature samples and respective sets of the second equalizer coefficients less the second training sequence.
6. The method of claim 5 wherein the deriving second equalizer coefficients further comprises performing the second MSE solution at a plurality of time trials and evaluating a second performance metric to select a time reference for the second plurality of equalizer filters.
7. The method of claim 1 wherein the processing the in phase samples and the quadrature samples further comprises combining outputs from the first plurality of equalizer filters to provide first demodulated symbols and combining outputs from the second plurality of equalizer filters to provide second demodulated symbols.
8. The method of claim I wherein the sampled signal includes a first sampled signal from a first receiver input and a second sampled signal from a second receiver input and the separating a sampled signal includes separating the first and second sampled signal into respective first and second in phase and quadrature samples and wherein the second in phase and quadrature samples are used for deriving third and fourth equalizer coefficients used for programming a third and fourth plurality of equalizer filters with these filters used for processing the second in phase and quadrature samples, respectively to provide second demodulated symbols, wherein the demodulated symbols and the second demodulated symbols are combined to provide improved demodulated symbols.
9. A method of providing an orthogonal modulated signal using a plurality of bit streams, the method comprising:
providing a first bit stream and providing a second bit stream;
converting, in a first processor, the first bit stream to first in phase symbols and the second bit stream to second in phase symbols;
generating, in a second processor, a complex orthogonal modulated signal by orthogonally combining respective ones of the first in phase symbols and the second in phase symbols.
10. The method of claim 9 wherein the generating a complex orthogonal modulated signal further comprises weighting each of the first in phase symbols and each of the second in phase samples with respective first and second weights.
11. The method of claim 9 wherein the generating a complex orthogonal modulated signal further comprises multiplying each of the second in phase samples by the quadrature operator to thereby provide the orthogonality between the first and second in phase samples.
12. The method of claim 9 wherein the converting the first bit stream to first in phase symbols and the second bit stream to second in phase symbols further comprises assigning symbols using independent quaternary modulation.
13. The method of claim 12 wherein the assigning symbols using independent quaternary modulation further comprises independently assigning one of four real value symbols to each pair of bits in the first bit stream and in the second bit stream.
14. The method of claim 9 further comprising inserting a first training symbol sequence in the first in phase symbols and a second training symbol sequence in the second in phase symbols.
15. The method of claim 9 further comprising inserting a first and a second training symbol sequence, respectively in the first and second in phase symbols;
wherein the converting the first bit stream to first in phase symbols and the second bit stream to second in phase symbols further comprises assigning symbols using independent quaternary modulation, which further comprises independently assigning one of four real value symbols to each pair of bits in the first bit stream and in the second bit stream;
wherein the generating a complex orthogonal modulated signal further comprises weighting each of the first and second in phase symbols with respective first and second weights and multiplying each of the second in phase samples by the quadrature operator, thereby providing orthogonality between the first and second in phase samples, and
then sequentially selecting each of the first in phase symbols and corresponding each of the second in phase symbols as multiplied by the quadrature operator to provide the in phase and quadrature portions of a complex orthogonal modulated symbol.
16. A receiver for demodulating an orthogonal modulated signal, the receiver comprising:
an analog to digital converter (ADC) for converting a modulated signal to a sampled signal with in phase samples and quadrature samples; and
a processor circuitry coupled to the ADC and arranged and configured to:
separate the sampled signal into in phase samples and quadrature samples, the sampled signal corresponding to the orthogonal modulated signal;
derive first equalizer coefficients and second equalizer coefficients based on corresponding in phase samples and corresponding quadrature samples and further, respectively, based on a first training sequence and on a second training sequence;
program a first plurality of equalizer filters with the first equalizer coefficients and a second plurality of equalizer filters with the second equalizer coefficients; and
process, after the programming, the in phase samples and the quadrature samples through the first and second plurality of equalizer filters to provide demodulated symbols.
17. The receiver of claim 16 wherein the receiver further comprises a de-rotator to de-rotate the sampled signal on a sample by sample basis prior to the separating into in phase and quadrature samples.
18. The receiver of claim 16 wherein the processor circuitry is further arranged and configured to derive the first equalizer coefficients by further performing a first Minimum Square Error (MSE) solution to a convolution of the in phase and the quadrature samples and respective sets of the first equalizer coefficients less the first training sequence.
19. The receiver of claim 18 wherein the processor circuitry is further arranged and configured to derive the first equalizer coefficients by further performing the first MSE solution at a plurality of time trials and evaluating a performance metric to select a time reference for the first plurality of equalizer filters.
20. The receiver of claim 18 wherein the processor circuitry is further arranged and configured to derive the second equalizer coefficients by further performing a second Minimum Square Error (MSE) solution to a convolution of the in phase and the quadrature samples and respective sets of the second equalizer coefficients less the second training sequence.
21. The receiver of claim 20 wherein the processor circuitry is further arranged and configured to derive the second equalizer coefficients by further performing the second MSE solution at a plurality of time trials and evaluating a second performance metric to select a time reference for the second plurality of equalizer filters.
22. The receiver of claim 16 wherein the processor circuitry is further arranged and configured to process the in phase samples and the quadrature samples by further combining outputs from the first plurality of equalizer filters to provide first demodulated symbols and combining outputs from the second plurality of equalizer filters to provide second demodulated symbols.
23. The receiver of claim 16 further comprising:
a second ADC coupled to a second receiver input for converting a second modulated signal to a second sampled signal with second in phase samples and second quadrature samples,
a second processor circuitry coupled to the second ADC and arranged and configured to duplicate the operations of the processor circuitry after substituting the second in phase samples for the in phase samples and after substituting the second quadrature samples for the quadrature samples to provide second demodulated symbols; and
additional combiners to combine the demodulated symbols and second demodulated symbols to provide improved demodulated symbols.