Granted Patent B2

US 9,097,758 · App. 13/255,523 · Granted Aug 4, 2015

Abstract

Claims (52)

1. An integrated circuit device comprising

a semiconductor die and

a package attached to the semiconductor die, the package including a plurality of terminals including a power supply terminal and a ground terminal,

wherein said semiconductor die includes

a power supply node coupled to said power supply terminal adapted to receive a supply voltage, and

an internal connection verification module comprising a voltage comparator that determines a first voltage difference between said power supply node and a reference voltage, and asserts a poor connection signal when said first voltage difference is indicative of a poor connection between said power supply node and said power supply terminal,

wherein said reference voltage includes a supply reference voltage associated with the supply voltage and a ground reference voltage associated with a supply ground, and,

wherein said internal test connection verification module asserts said poor connection signal in response to

a second voltage difference between said supply voltage at said voltage supply node and said supply reference voltage, and to

a third voltage difference between said ground at said ground node and said ground reference voltage.

2. The integrated circuit device of claim 1 , wherein said internal test connection verification module includes a register including a register output for registering assertion of said poor connection signal.

3. The integrated circuit device of claim 1 , wherein said power supply terminal includes a solder ball contact.

4. The integrated circuit of claim 1 , wherein the voltage comparator comprises a first input coupled to said power supply node, a second input coupled to said reference voltage, and an output to provide said poor connection signal.

5. The integrated circuit of claim 4 , wherein said internal connection verification module includes a peak detector including an input to receive the voltage signal, and an output for providing the reference voltage.

6. The integrated circuit of claim 4 , wherein said peak detector provides said reference voltage such that said reference voltage is a delayed version of said voltage signal at a first time when said voltage signal is indicative of a first load of said semiconductor die at said first time, and said voltage signal provided at said first input of said comparator is indicative of a second load of said semiconductor die at a second time, wherein the first load corresponds to lower circuit activity, and the second load corresponds to higher circuit activity.

7. The integrated circuit of claim 4 , wherein said reference voltage is provided internally from said semiconductor die.

8. The integrated circuit of claim 7 , wherein said reference voltage is provided from an unloaded power domain of said semiconductor die.

9. The integrated circuit of claim 4 , wherein said reference voltage is provided via an external test apparatus.

10. A method comprising:

receiving, at a first input terminal of a voltage comparator of an internal connection verification module of a semiconductor die of an integrated circuit device, a voltage signal from a power supply node of the semiconductor die,

receiving, at an input terminal of a peak detector of the internal connection verification module, the voltage signal,

providing, at an output terminal of the peak detector, a delayed version of the voltage signal to a second input terminal of the voltage comparator,

determining, by the voltage comparator, that a voltage difference between the voltage signal and the delayed version of the voltage signal is indicative of a poor connection between said power supply node and a power supply terminal of a package, wherein the power supply terminal is coupled to the power supply node, and wherein said integrated circuit device includes said semiconductor die included on said package; and

asserting, at an output node of the voltage comparator, a poor connection signal in response to the determination.

11. The method of claim 10 , further comprising:

determining to reject said integrated circuit device in response to asserting said poor connection signal.

12. The method of claim 10 , wherein said voltage difference is a difference between a first voltage at said power supply node at a first time at which a first power consumption of said semiconductor die is different from a second voltage at said power supply node at a second time wherein said semiconductor die has a second power consumption, wherein the first power consumption corresponds to lower circuit activity, and the second power consumption corresponds to higher circuit activity.

13. The method of claim 10 , wherein said voltage difference is a difference between a voltage at said corresponding node and a voltage at a position in said integrated circuit device which is less affected by supply current consumption of said semiconductor die.

14. The method of claim 10 , further comprising:

applying logic signals to, and detecting logic signals from, logic signal terminals of said integrated circuit device; and

supplying power to said integrated circuit device during test through a contact to said power supply terminal.

15. The method of claim 10 , further comprising:

mounting said integrated circuit device on a support;

applying logic signals to, and detecting logic signals from, logic signal terminals of said integrated circuit device through said support; and

supplying power for said integrated circuit device during test through said support to said power supply terminal.

16. The method of claim 10 , wherein, in determining that said voltage difference is indicative of said poor connection signal, the method further comprises:

providing a voltage signal from said power supply node to a first input of a comparator;

providing the reference signal to a second input of said comparator; and

asserting said poor connection signal via an output of said comparator.

17. The method of claim 16 , wherein, in determining that said voltage difference is indicative of said poor connection signal, the method further comprises:

providing said voltage signal to an input of a peak detector; and

providing said reference voltage via an output of said peak detector.

18. The method of claim 16 , wherein said reference voltage is provided internally from said semiconductor die.

19. The method of claim 16 , wherein said reference voltage is provided via an external test apparatus.

20. An integrated circuit device comprising

a semiconductor die and

a package attached to the semiconductor die, the package including a plurality of terminals including a power supply terminal,

wherein said semiconductor die includes

a power supply node coupled to said power supply terminal and

an internal connection verification module comprising,

a voltage comparator including a first input coupled to said power supply node, a second input coupled to reference voltage, and an output to provide said poor connection signal, wherein said voltage comparator determines a first voltage difference between said power supply node and a reference voltage, and asserts a poor connection signal when said first voltage difference is indicative of a poor connection between said power supply node and said power supply terminal, and

a peak detector including an input to receive the voltage signal, and an output for providing the reference voltage, wherein said peak detector provides said reference voltage such that said reference voltage is a delayed version of said voltage signal at a first time when said voltage signal is indicative of a first load of said semiconductor die at said first time, and said voltage signal provided at said first input of said comparator is indicative of a second load of said semiconductor die at a second time, wherein the first load corresponds to lower circuit activity, and the second load corresponds to higher circuit activity.

Assignments (32)