Dynamic pad size to reduce solder fatigue
View Patent ↗A semiconductor device is provided which comprises a substrate ( 501 ) having a plurality of bond pads ( 503 ) disposed thereon. Each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and the ratio of the major axis to the minor axis increases with the distance of a bond pad from the center of the substrate.
1. A semiconductor device, comprising:
a substrate having a plurality of bond pads disposed thereon;
wherein each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and wherein the ratio of the major axis to the minor axis increases with the distance of a bond pad from the center of the substrate;
wherein each bond pad has a solder joint attached thereto, and wherein the dimension of the bond pad in any direction in the plane is proportional to the relative strain experienced by the solder joint in that direction.
2. The semiconductor device of claim 1 , wherein the ratio of the major axis to the minor axis of each of said plurality of bond pads is essentially proportional to the distance of the bond pad from the center of the substrate.
3. The semiconductor device of claim 2 , further comprising a die disposed on said substrate, and where the ratio d s of the major axis to the minor axis of any of said plurality of bond pads is essentially given by the equation
d s =Δ CTE *L
wherein L is the distance from the center of the substrate, and wherein Δ CTE is the CTE stress differential between the die and the substrate.
4. The semiconductor device of claim 3 , where Δ CTE is given by the equation
Δ CTE =ΔT *( CTE substrate −CTE die )
wherein
ΔT is the temperature range to which the device is exposed;
CTE substrate is the coefficient of thermal expansion of the substrate; and
ΔCTE die is the coefficient of thermal expansion of the die.
5. The semiconductor device of claim 1 , wherein each of said plurality of bond pads is essentially elliptical in shape.
6. The semiconductor device of claim 1 , wherein the semiconductor device is a flip-chip device.
7. The semiconductor device of claim 1 , wherein the semiconductor device includes flip-chip packaging.
8. The semiconductor device of claim 1 , wherein the major axis of each bond pad is essentially parallel to the major axis of thermal expansion of the solder joint in a direction parallel to the substrate.
9. The semiconductor device of claim 1 , wherein the substrate has a layer of solder resist disposed thereon, and wherein the plurality of bond pads is formed by a process that includes selectively removing portions of the solder resist.
10. The semiconductor device of claim 1 , wherein the substrate is a packaging substrate, and wherein each solder joint is attached on a first end to one of said plurality of bond pads, and is attached on a second end to a semiconductor die.
11. The semiconductor device of claim 1 , wherein the solder joints are formed from a ball grid array.
12. The semiconductor device of claim 1 , further comprising a solder mask.
13. The semiconductor device of claim 12 , wherein each bond pad has a solder mask opening associated with it.
14. The semiconductor device of claim 1 , wherein the substrate is a ball grid array (BGA).
15. The semiconductor device of claim 14 , further comprising a die.
16. The semiconductor device of claim 15 , wherein the die and BGA are connected by a plurality of solder joints, and wherein one end of each solder joint is attached to a bond pad disposed on said BGA.
17. The semiconductor device of claim 16 , wherein each solder joint formed to the BGA substrate is solder mask-defined (SMD).
18. The semiconductor device of claim 16 , wherein each solder joint formed to the die is non-solder mask-defined (NSMD).
19. A semiconductor device, comprising:
a substrate having a plurality of bond pads disposed thereon, wherein each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and wherein the ratio of the major axis to the minor axis increases with the distance of a bond pad from the center of the substrate; and
a die disposed on said substrate;
wherein the ratio d s of the major axis to the minor axis of any of said plurality of bond pads is essentially given by the equation
d s =Δ CTE *L
wherein L is the distance from the center of the substrate, wherein Δ CTE is the CTE stress differential between the die and the substrate, and wherein the ratio of the major axis to the minor axis of each of said plurality of bond pads is essentially proportional to the distance of the bond pad from the center of the substrate.
20. The semiconductor device of claim 19 , where Δ CTE is given by the equation
Δ CTE =ΔT *( CTE substrate −CTE die )
wherein
ΔT is the temperature range to which the device is exposed;
CTE substrate is the coefficient of thermal expansion of the substrate; and
ΔCTE die is the coefficient of thermal expansion of the die.