Granted Patent B2

US 8,877,601 · App. 12/886,859 · Granted Nov 4, 2014

Abstract

Claims (31)

1. A method for forming a semiconductor structure, comprising:

forming an active device region in and on a semiconductor substrate;

forming an interconnect layer over the active device region, wherein the interconnect layer comprises a first dielectric material having a first dielectric constant, a first metal interconnect in the first dielectric material, and a second metal interconnect in the first dielectric material and laterally spaced apart from the first metal interconnect;

removing a portion of the first dielectric material such that a remaining portion of the first dielectric material remains within the interconnect layer, wherein the removed portion is removed from a location between the first and second metal interconnects; and

filling the location between the first and second metal interconnects from which the portion of the first dielectric material was removed with a second dielectric material having a second dielectric constant, the second dielectric constant being higher than the first dielectric constant, wherein the step of filling comprises:

depositing a layer of the second dielectric material over the interconnect layer; and

removing portions of the layer of the second dielectric material which extend above the interconnect layer such that a remaining portion of the layer of the second dielectric material remains over each of the first and second metal interconnects; and

forming a second interconnect layer over the remaining portion of the layer of the second dielectric material, wherein the remaining portion of the layer of the second dielectric material is between the second interconnect layer and each of the first and second metal interconnects.

2. The method of claim 1 , wherein the interconnect layer comprises a third metal interconnect in the first dielectric material laterally spaced apart from the first metal interconnect, and wherein the step of removing the portion of the first dielectric material is performed such that the removed portion is also removed from a second location between the second and third metal interconnects.

3. The method of claim 2 , wherein the step of filling comprises filling the second location between the second and third metal interconnects with the second dielectric material.

4. The method of claim 3 , wherein the step of forming the interconnect layer comprises forming a lateral capacitor in the interconnect layer, wherein the first, second, and third metal interconnects are electrodes of the lateral capacitor.

5. The method of claim 4 , wherein the step of forming the interconnect layer comprises forming a first and a second lateral capacitor in the interconnect layer, wherein the first and second metal interconnects are electrodes of the first lateral capacitor and the second and third metal interconnects are electrodes of the second lateral capacitor.

6. The method of claim 1 , wherein the step of removing the portion of the first dielectric material is performed from a capacitor region of the interconnect layer and the remaining portion remains in a lower dielectric constant region of the interconnect layer.

7. The method of claim 1 , wherein the step of forming the interconnect layer comprises forming a lateral capacitor in the interconnect layer, wherein the first and second metal interconnects are electrodes of the lateral capacitor.

8. The method of claim 1 , wherein the step of forming the interconnect layer is further characterized in that the interconnect layer further comprises a continuous ring of metal which surrounds the first and second metal interconnects.

9. The method of claim 8 , wherein after the step of filling the location between the first and second metal interconnects, the continuous ring of metal is located between the first dielectric material and the second dielectric material.

10. The method of claim 1 , wherein the step of forming the interconnect layer comprises:

forming a via-level portion of the interconnect layer over the active device region;

forming an etch stop layer over the via-level portion; and

forming a trench-level portion of the interconnect layer over the etch stop layer, wherein the trench-level portion comprises the first dielectric material, and the first and second metal interconnects.

11. The method of claim 10 , wherein the step of removing the portion of the first dielectric material is performed using the etch stop layer such that the removed portion is removed from the location between the first and second metal interconnects in the trench-level portion.

12. A method for forming a semiconductor structure, comprising:

forming an active device region in and on a semiconductor substrate;

forming a first dielectric layer of a first dielectric material over the active device region, wherein the first dielectric material has a first dielectric constant;

forming an etch stop layer over the first dielectric layer;

forming a second dielectric layer of a second dielectric material over the etch stop layer, wherein the second dielectric material has a second dielectric constant;

forming a plurality of conductive vias in the first dielectric layer and a plurality of metal interconnects in the second dielectric layer, wherein the second dielectric layer and the plurality of metal interconnects are further characterized as a trench-level portion of an interconnect layer, wherein each of the plurality of metal interconnects is laterally spaced apart from each other and wherein the plurality of metal interconnects form at least one lateral capacitor;

removing a portion of the second dielectric material from the trench-level portion of the interconnect layer using the etch stop layer such that the removed portion is removed from locations above the etch-stop layer and between laterally adjacent metal interconnects of the plurality of metal interconnects and a remaining portion of the second dielectric material remains within the trench-level portion of the interconnect layer; and

filling the locations between the laterally adjacent metal interconnects from which the portion of the second dielectric material was removed with a third dielectric material having a third dielectric constant, the third dielectric constant being higher than the second dielectric constant.

13. The method of claim 12 , wherein the plurality of metal interconnects form inter-digitated electrodes of a first lateral capacitor.

14. The method of claim 12 , wherein the plurality of metal interconnects form electrodes of multiple lateral capacitors.

Assignments (18)