Bond pad for semiconductor die
View Patent ↗A semiconductor die has rows of bond pads along the edges of a major surface. The corners of the die are designated as keep out areas, with design layout rules prohibiting a probe-able bond pad from being placed in the keep out areas so that a minimum distance may be maintained between distal ends of adjacent rows of bond pads (i.e., bond pads along adjacent edges). The bond pads of each row have IO pad areas that are aligned with each other and IO probe areas that are aligned with each other. A generally L-shaped bond pad includes a first, vertical part that extends inwardly from an edge of the semiconductor die and a second, horizontal part connected to the vertical part. The L-shaped bond pad may be placed between a last bond pad in a row and a corner keep out area, and the second part of the L-shaped bond pad extends into the corner keep out area. The first part has an IO pad area that is in alignment with the IO pad areas of the other bond pads in the same row, and the second part has an IO probe area that is in alignment with the IO probe areas of the bond pads in the adjacent row. The L-shaped bond pad does not violate design rules even though a part of the pad extends into the corner keep out area.
1. A semiconductor die, comprising:
a first row of bond pads disposed along a first edge of the device;
a second row of bond pads disposed along a second edge of the device, wherein the second row is perpendicular to the first row;
wherein each bond pad includes at least an input/output (IO) pad area for providing an IO connection to circuitry of the device and an IO probe area for receiving a tip of a test probe;
wherein the IO pad areas of the bond pads of the first row are aligned with each other, the IO probe areas of the bond pads of the first row are aligned with each other, and the IO probe areas of the bond pads of the second row are aligned with each other;
a first corner keep out area, located between the first and second rows at a first corner of the device, wherein design layout rules specify that a bond pad that is to be probed cannot be placed in the first corner keep out area; and
a first L-shaped additional bond pad located between the first corner keep out area and a first bond pad in the first row of bond pads, wherein the additional bond pad has an IO pad area that is aligned with the IO pad areas of the bond pads of the first row and an IO probe area that is aligned with the IO probe areas of the bond pads of the second row, and wherein the IO probe area extends into the first corner keep out area.
2. The semiconductor die of claim 1 , wherein a predetermined minimum distance between the IO probe area of the first bond pad in the first row and the IO probe areas of the bond pads of the second row of bond pads and the additional bond pad is maintained.
3. The semiconductor die of claim 1 , wherein the bond pads of the first row of bond pads have a proximal end adjacent to the first edge and a distal end spaced from the first edge, and wherein the IO pad areas are proximate to the centers of the bond pads and the IO probe areas are located at the distal ends of the bond pads.
4. The semiconductor die of claim 3 , wherein the bond pads of the second row of bond pads have a proximal end adjacent to the second edge and a distal end spaced from the second edge, and wherein the IO pad areas are proximate to the centers of the bond pads and the IO probe areas are located at the distal ends of the bond pads.
5. The semiconductor die of claim 4 , wherein the bond pads of the first and second rows include an embedded power and ground (PGE) pad area and a PGE probe area.
6. The semiconductor die of claim 5 , wherein the PGE probe areas are located at the proximal ends of the bond pads and the PGE pad areas are located between the PGE probe areas and the IO pad areas.
7. The semiconductor die of claim 6 , wherein the first additional bond pad has a PGE pad area that is aligned with the PGE pad areas of the bond pads of the first row, and a PGE probe area that is aligned with the PGE probe areas of the bond pads of the first row.
8. The semiconductor die of claim 1 , further comprising:
a third row of bond pads disposed along a third edge of the device, wherein the third edge is perpendicular to the first edge;
a second corner keep out area, located between the first and third rows at a second corner of the device, wherein the design layout rules specify that a bond pad that is to be probed cannot be placed in the second corner keep out area;
wherein each bond pad of the third row of bond pads includes at least an IO pad area for providing an IO connection to the device circuitry and an IO probe area for receiving a tip of a test probe;
wherein the IO pad areas of the bond pads of the third row are aligned with each other and the IO probe areas of the bond pads of the third row are aligned with each other; and
a second L-shaped additional bond pad located between the second corner keep out area and a last bond pad in the first row of bond pads, wherein the second additional bond pad has an IO pad area that is aligned with the IO pad areas of the bond pads of the first row and an IO probe area that is aligned with the IO probe areas of the bond pads of the third row, and wherein the IO probe area extends into the second corner keep out area.
9. The semiconductor die of claim 8 , wherein
a first predetermined minimum distance between the IO probe area of the first bond pad in the first row and the IO probe areas of the bond pads of the second row of bond pads and the first additional bond pad is maintained,
a second predetermined minimum distance between the IO probe area of the last bond pad in the first row and the IO probe areas of the bond pads of the third row of bond pads and the second additional bond pad is maintained, and wherein the first predetermined minimum distance equals the second predetermined minimum distance.
10. The semiconductor die of claim 9 , further comprising:
a fourth row of bond pads disposed along a fourth edge of the device, wherein the fourth edge is adjacent and perpendicular to the second and third edges;
third and fourth corner keep out areas, respectively located between the second and fourth edges at a third corner of the device and between the third and fourth edges at a fourth corner of the device, wherein the design layout rules specify that a bond pad that is to be probed, cannot be placed in either of the third or fourth corner keep out areas;
wherein each bond pad of the fourth row of bond pads includes at least an IO pad area for providing an IO connection to the device circuitry and an IO probe area for receiving a tip of a test probe, and wherein the IO pad areas of the bond pads of the fourth row are aligned with each other and the IO probe areas of the bond pads of the fourth row are aligned with each other;
a third L-shaped additional bond pad located between the third corner keep out area and a first bond pad in the fourth row of bond pads, wherein the third additional bond pad has an IO pad area that is aligned with the IO pad areas of the bond pads of the fourth row and an IO probe area that is aligned with the IO probe areas of the bond pads of the second row, and wherein the IO probe area extends into the third corner keep out area; and
a fourth L-shaped additional bond pad located between the fourth corner keep out area and a last bond pad in the fourth row of bond pads, wherein the fourth additional bond pad has an IO pad area that is aligned with the IO pad areas of the bond pads of the fourth row and an IO probe area that is aligned with the IO probe areas of the bond pads of the third row, and wherein the IO probe area extends into the fourth corner keep out area.
11. A semiconductor die, comprising:
a first row of bond pads disposed along a first edge of the device;
a second row of bond pads disposed along a second edge of the device, wherein the second row is perpendicular to the first row;
a third row of bond pads disposed along a third edge of the device, wherein the third row is perpendicular to the first row and parallel to the second row;
a fourth row of bond pads disposed along a fourth edge of the device, wherein the fourth row is parallel to the first row and perpendicular to the second and third rows;
wherein each bond pad includes at least an input/output (IO)) pad area for providing an IO connection to circuitry of the device and an IO probe area for receiving a tip of a test probe;
wherein the IO pad areas of each row are aligned with the other IO pad areas of the same row and the IO probe areas of each row are aligned with the other IO probe areas of the same row;
first, second, third and fourth corner keep out areas respectively located in each of the four corners of the semiconductor die, wherein design layout rules specify that bond pads to be probed cannot be placed in the corner keep out areas; and
a first L-shaped additional bond pad located between the first corner keep out area and a first bond pad in the first row of bond pads, wherein the additional bond pad has an IO pad area that is aligned with the IO pad areas of the bond pads of the first row and an IO probe area that is aligned with the IO probe areas of the bond pads of the second row, and wherein the IO probe area extends into the first corner keep out area;
a second L-shaped additional bond pad located between the second corner keep out area and a last bond pad in the first row of bond pads, wherein the second additional bond pad has an IO pad area that is aligned with the IO pad areas of the bond pads of the first row and an IO probe area that is aligned with the IO probe areas of the bond pads of the third row, and wherein the IO probe area extends into the second corner keep out area;
a third L-shaped additional bond pad located between the third corner keep out area and a first bond pad in the fourth row of bond pads, wherein the third additional bond pad has an IO pad area that is aligned with the IO pad areas of the bond pads of the fourth row and an IO probe area that is aligned with the IO probe areas of the bond pads of the second row, and wherein the IO probe area extends into the third corner keep out area; and
a fourth L-shaped additional bond pad located between the fourth corner keep out area and a last bond pad in the fourth row of bond pads, wherein the fourth additional bond pad has an IO pad area that is aligned with the IO pad areas of the bond pads of the fourth row and an IO probe area that is aligned with the IO probe areas of the bond pads of the third row, and wherein the IO probe area extends into the fourth corner keep out area.
12. The semiconductor die of claim 11 , wherein
a predetermined minimum distance between the IO probe area of the first bond pad in the first row and the IO probe areas of the bond pads of the second row of bond pads and the first additional bond pad is maintained,
the predetermined minimum distance is maintained between the IO probe area of the last bond pad in the first row and the IO probe areas of the bond pads of the third row of bond pads and the second additional bond pad,
the predetermined minimum distance is maintained between the IO probe area of the first bond pad in the fourth row and the IO probe areas of the bond pads of the second row of bond pads and the third additional bond pad, and
the predetermined minimum distance is maintained between the IO probe area of the last bond pad in the fourth row and the IO probe areas of the bond pads of the third row of bond pads and the fourth additional bond pad.
13. An additional bond pad for a semiconductor die, wherein the semiconductor die has first and second major surfaces and four sides, keep out areas in the four corners of the first major surface, wherein design rules specify that bond pads are not to be placed within the corner keep out areas, and a plurality of rows of generally rectangular bond pads, each row located along respective sides on the first major surface between respective corner keep out areas, wherein the bond pads have an IO pad area proximate a central part thereof and a probe area at a distal end thereof, and wherein the IO pad areas of each row are aligned and the probe areas of each row are aligned, the additional bond pad comprising:
a first, vertical section having a proximal end that extends from one of the sides of the semiconductor die inwardly to a distal end, wherein the vertical section is located between one of the corner keep out areas and an adjacent bond pad, and wherein the first section has an IO pad area at the distal end thereof that is aligned with the IO pad areas of the bond pads in the same row; and
a second, horizontal section that abuts the distal end of the first section and extends away from the first section toward and into the adjacent corner keep out area, the second section having a probe area at a distal end thereof that is aligned with the probe areas of bond pads in an adjacent row.
14. The additional bond pad of claim 13 , wherein the first and second sections form an L-shape.
15. The additional bond pad of claim 13 , wherein a predetermined minimum distance is maintained between the IO probe area of a first bond pad in a first one of the rows and the IO probe areas of the bond pads of an adjacent row of bond pads, including the IO probe area of the additional bond pad.
16. The additional bond pad of claim 13 , wherein the first vertical section includes an embedded power ground (PGE) area and a PGE probe area.