Granted Patent B2

US 8,202,778 · App. 12/872,073 · Granted Jun 19, 2012

Abstract

Claims (48)

1. A method for forming a gate stack of a non-volatile memory (NVM) over a semiconductor substrate having an NVM region and a non-NVM region which does not overlap the NVM region, the method comprising:

forming a select gate layer over the substrate in the NVM region and the non-NVM region;

simultaneously etching the select gate layer in the NVM region and the select gate layer in the non-NVM region, wherein the etching the select gate layer in the NVM region results in a first portion of the select gate layer remaining in the NVM region;

forming a charge storage layer over the substrate in the NVM region and the non-NVM region, wherein the charge storage layer is formed over the first portion of the select gate layer;

forming a control gate layer over the charge storage layer in the NVM region and the non-NVM region;

simultaneously etching the control gate layer in the NVM region and the non-NVM region;

simultaneously etching the charge storage layer in the NVM region and the non-NVM region, wherein the etching the select gate layer in the NVM region results in a portion of the charge storage layer over the first portion of the select gate layer and overlapping a sidewall of the first portion of the select gate layer and results in a portion of the control gate layer over the portion of the charge storage layer; and

forming a split gate device using the first portion of the select gate layer, the portion of the charge storage layer, and the portion of the control gate layer.

2. The method of claim 1 , wherein the select gate layer in the non-NVM region is formed over a tiling feature.

3. The method of claim 1 , wherein the select gate layer in the non-NVM region is formed over an active circuit feature.

4. The method of claim 1 , wherein the step of etching the select gate layer in the non-NVM region results in a second portion of the select gate layer remaining in the non-NVM region.

5. The method of claim 4 , wherein the second portion is further characterized as a dummy feature.

6. The method of claim 5 , wherein, the steps of etching the charge storage layer and the control gate layer in the non-NVM region are performed such that a top surface of the dummy feature is exposed.

7. The method of claim 4 , wherein the second portion is further characterized as an active circuit feature.

8. The method of claim 1 , wherein the step of simultaneously etching the select gate layer in the NVM region and the select gate layer in the non-NVM region is performed such that the select gate is completely removed from the non-NVM region.

9. The method of claim 1 , wherein the semiconductor substrate comprises a logic region, and wherein:

the step of forming the select gate layer is performed such that the select gate layer is formed over the substrate in the logic region,

the step of forming the charge storage layer is performed such that the charge storage layer is formed over the select gate layer in the logic region, and

the step of forming the control gate layer is performed such that the control gate layer is formed over the charge storage layer in the logic region.

10. The method of claim 9 , wherein the step of simultaneous etching the select gate layer in the NVM region and the select gate layer in the non-NVM region does not etch the select gate layer in the logic region.

11. The method of claim 10 , wherein:

the step of simultaneously etching the control gate layer is performed such that the control gate layer is removed from the logic region, and

the step of simultaneously etching the charge storage layer is performed such that the charge storage layer is removed from the logic region.

12. The method of claim 11 , wherein after the step of simultaneously etching the charge storage layer, patterning the select gate layer in the logic region to form a logic device gate.

13. A method for forming a gate stack of a non-volatile memory (NVM) over a semiconductor substrate having an NVM region and a non-NVM region which does not overlap the NVM region, the method comprising:

forming a select gate layer over the substrate in the NVM region and the non-NVM region, wherein the select gate layer is formed over a tiling feature;

simultaneously etching the select gate layer in the NVM region and the select gate layer in the non-NVM region, wherein the etching the select gate layer in the non-NVM region exposes the tiling feature and the etching the select gate layer in the NVM region results in a first portion of the select gate layer remaining in the NVM region;

forming a charge storage layer over the substrate in the NVM region and the non-NVM region, wherein the charge storage layer is formed over the first portion of the select gate layer;

forming a control gate layer over the charge storage layer in the NVM region and the non-NVM region;

simultaneously etching the control gate layer in the NVM region and the non-NVM region;

simultaneously etching the charge storage layer in the NVM region and the non-NVM region, wherein the etching the charge storage layer and the control gate layer in the non-NVM region exposes the tiling feature and the etching the select gate layer in the NVM region results in a portion of the charge storage layer over the first portion of the select gate layer and overlapping a sidewall of the first portion of the select gate layer and results in a portion of the control gate layer over the portion of the charge storage layer; and

forming a split gate device using the first portion of the select gate layer, the portion of the charge storage layer, and the portion of the control gate layer.

14. The method of claim 13 , wherein the step of etching the select gate layer in the non-NVM region results in a second portion of the select gate layer remaining in the non-NVM region, wherein the second portion is further characterized as a dummy feature.

15. The method of claim 14 , wherein, the steps of etching the charge storage layer and the control gate layer in the non-NVM region are performed such that a top surface of the dummy feature is exposed.

16. The method of claim 14 , wherein the dummy feature is formed over the tiling feature.

17. A method for forming a gate stack of a non-volatile memory (NVM) over a semiconductor substrate having an NVM region, a non-NVM region which does not overlap the NVM region, and a logic region, the method comprising:

forming a select gate layer over the substrate in the NVM region, the non-NVM region, and the logic region;

simultaneously etching the select gate layer in the NVM region and the select gate layer in the non-NVM region, wherein the etching the select gate layer in the NVM region results in a first portion of the select gate layer remaining in the NVM region;

forming a charge storage layer over the substrate in the NVM region, the non-NVM region, and the logic region, wherein the charge storage layer is formed over the first portion of the select gate layer;

forming a control gate layer over the charge storage layer in the NVM region, the non-NVM region, and the logic region;

simultaneously etching the control gate layer in the NVM region, the non-NVM region, and the logic region;

simultaneously etching the charge storage layer in the NVM region, the non-NVM region, and the logic region, wherein the etching the select gate layer in the NVM region results in a portion of the charge storage layer over the first portion of the select gate layer and overlapping a sidewall of the first portion of the select gate layer and results in a portion of the control gate layer over the portion of the charge storage layer;

forming a split gate device using the first portion of the select gate layer, the portion of the charge storage layer, and the portion of the control gate layer; and

forming a logic device gate using the select gate layer in the logic region.

18. The method of claim 17 , wherein the step of forming the logic device gate comprises:

after the step of simultaneously etching the charge storage layer, patterning the select gate layer in the logic region to form the logic device gate.

19. The method of claim 17 , wherein the step of simultaneous etching the select gate layer in the NVM region and the select gate layer in the non-NVM region does not etch the select gate layer in the logic region.

20. The method of claim 17 , wherein the step of forming the select gate layer over the substrate in the non-NVM region is performed such that the select gate layer is formed over an active circuit feature in the non-NVM region.

Assignments (21)