Granted Patent B2

US 8,338,828 · App. 12/851,527 · Granted Dec 25, 2012

Abstract

Claims (21)

1. A semiconductor package, comprising:

a substrate;

a plurality of electrical conductors on a surface of the substrate for conducting electrical current between a die and a plurality of solderballs; and

a protective layer formed on the surface of the substrate for protecting the electrical conductors, the protective layer comprising a test electrical conductor, wherein the protective layer has plural peripheral edges and the test electrical conductor forms a loop, at least a substantial portion thereof being disposed proximate the plural peripheral edges.

2. The semiconductor package of claim 1 , wherein the test electrical conductor comprises a first and second ends, each of which are connected to copper pad terminals for application of a voltage thereto.

3. The semiconductor package of claim 1 , wherein the test electrical conductor comprises a first end and a second end, the first end being connected to a first via in the substrate and the second end being connected to a second via in the substrate, the first via and the second via each being arranged for connection to respective solderballs.

4. The semiconductor package of claim 1 , wherein the substrate has a first region in which terminals for the plurality of electrical conductors are disposed, and the protective layer has a second region disposed adjacent the first region, at least a part of the test electrical conductor being disposed proximate the second region.

5. The semiconductor package of claim 4 , wherein the test electrical conductor forms a loop around at least a part of the second region.

6. A semiconductor package, comprising:

a substrate;

a plurality of electrical conductors on a surface of the substrate for conducting electrical current between a die and a plurality of solder balls; and

a protective layer formed on the surface of the substrate for protecting the electrical conductors, the protective layer comprising first and second test electrical conductors, wherein the protective layer has a peripheral edge and at least a part of a first one of the first and second electrical conductors is disposed proximate the peripheral edge, and wherein the substrate has a first region in which terminals for the plurality of electrical conductors are disposed, and the protective layer has a second region disposed adjacent the first region, at least a part of a second one of the first and second electrical conductors being disposed proximate the second region.

7. An integrated circuit package, comprising:

a substrate including a wire layout pattern and a solder mask layer;

an integrated circuit attached to a surface of the substrate and electrically connected to the wire layout pattern;

encapsulating material covering at least the integrated circuit and the solder mask layer;

a plurality of crack seal rings formed on the solder mask surface, wherein the crack seal rings comprise copper traces, and wherein the plurality of crack seal rings includes a first ring, at least a portion of which is formed proximate an edge of the solder mask layer, for detecting solder mask cracks and a second ring, at least a portion of which is formed proximate the wire layout pattern, for detecting delamination between the encapsulation material and the solder mask surface; and

a plurality of terminals connected to the crack seal rings for permitting electrical connection to the crack seal rings.

8. The integrated circuit of claim 7 , wherein the plurality of crack seal rings are formed on the solder mask surface with a sputtering process.

9. The integrated circuit of claim 7 , wherein the plurality of terminals comprise solderballs.

10. The integrated circuit of claim 7 , wherein the plurality of terminals comprises plated copper pads.

Assignments (31)