Bipolar transistor and method with recessed base electrode
View Patent ↗High frequency performance of (e.g., silicon) bipolar devices is improved by reducing the extrinsic base resistance Rbx. An emitter, intrinsic base and collector are formed in a semiconductor body. An emitter contact has a region that overlaps a portion of an extrinsic base contact. A sidewall is formed in the extrinsic base contact proximate a lateral edge of the overlap region of the emitter contact. The sidewall is amorphized during or after formation so that when the emitter contact and the extrinsic base contact are, e.g., silicided, some of the metal atoms forming the silicide penetrate into the sidewall so that part of the highly conductive silicided extrinsic base contact extends under the edge of the overlap region of the emitter contact closer to the intrinsic base, thereby reducing R bx . Smaller R bx provides transistors with higher f MAX .
1. A method for forming a semiconductor device, comprising:
providing a semiconductor (SC) body;
forming an emitter, a base and a collector in the SC body;
forming a base contact on the SC body, the base contact having a proximate portion thereof ohmically coupled to the base;
forming an emitter contact ohmically coupled to the emitter and having an overlap region extending over the proximate portion;
removing part of the base contact beyond the overlap region thereby forming a sidewall in the base contact bordering the proximate portion; and
forming in the sidewall, a metal-semiconductor alloy region extending into the proximate portion under the overlap region.
2. The method of claim 1 , wherein the semiconductor body comprises silicon and the metal-semiconductor alloy region comprises a silicide.
3. The method of claim 1 , wherein the step of forming an emitter, a base and a collector comprises forming a hetero junction emitter-base region.
4. The method of claim 1 , wherein a mask is used to define the emitter contact and the overlap region thereof and the method further comprises:
using substantially the same mask during the step of removing part of the base contact.
5. The method of claim 1 , wherein the step of removing part of the base contact comprises, using the overlap region as a mask during the step of removing part of the base contact.
6. The method of claim 1 , further comprising prior to formation of the emitter contact, forming one or more sidewall spacers adapted to laterally separate the emitter contact from the base contact.
7. The method of claim 1 , wherein the step of forming on the sidewall, a metal-semiconductor alloy region extending into the proximate portion under the overlap region, occurs in part at or above about 100 degrees Celsius.
8. The method of claim 1 , wherein the step of forming on the sidewall, a metal-semiconductor alloy region extending into the proximate portion under the overlap region further comprises:
annealing at about 350 to 850 degrees Celsius for at least 5 seconds in a substantially inert gas; and then
etching to remove any un-reacted metal; and then
further annealing at about 350 to 900 degrees Celsius for at least 5 seconds.
9. The method of claim 1 , wherein prior to the step of forming on the sidewall, a metal-semiconductor alloy region extending into the proximate portion under the overlap region, the method further comprises, amorphizing part of the proximate portion adjacent the sidewall.
10. A method for forming a bipolar transistor, comprising:
forming an emitter region, a base region and a collector region in or on a semiconductor body;
providing a base contact, ohmically coupled to the base region, the base contact having a first portion proximate the base region, and a second portion separated from the first portion by a sidewall;
forming an emitter contact on the emitter region, the emitter contact having an overlap region overlapping the first portion of the base contact; and
forming a metal-semiconductor compound in the base contact, the metal-semiconductor compound extending from the sidewall into the first portion of the base contact and underlying at least part of the overlap region.
11. The method of claim 10 , further comprising, prior to formation of the metal-semiconductor compound, amorphizing the sidewall.
12. The method of claim 11 , wherein amorphizing the sidewall comprises bombarding the sidewall with inert gas ions.
13. The method of claim 12 , wherein bombarding the sidewall comprises implanting inert gas atoms into the sidewall using an angled implant at an angle α>0 with respect to a normal to a surface of the base contact.
14. The method of claim 10 , wherein the overlap region of the emitter contact has a distal edge, and wherein the sidewall of the base contact substantially underlies the distal edge.
15. The method of claim 10 , wherein the overlap region of the emitter contact has a distal edge, and wherein the sidewall of the base contact is recessed within respect to the distal edge.
16. The method of claim 10 , wherein the base contact has an inner terminal edge underlying the overlap region of the emitter contact, and wherein the first portion of the base contact is located between the inner terminal edge and the sidewall of the base contact.
17. The method of claim 10 , wherein providing a base contact comprises:
depositing a base electrode layer; and
etching away a portion of the base electrode layer to define a substantially vertical sidewall separating the base contact into the first and second portions.
18. The method of claim 17 , wherein the first portion of the base contact has a thickness greater than the second portion of the base contact.