Method for forming a split gate device
View Patent ↗A method for forming a semiconductor device includes forming a dielectric layer over a substrate. The method further includes forming a select gate layer over the dielectric layer. The method further includes etching the select gate layer at a first etch rate to form a first portion of a sidewall of a select gate, wherein the step of etching the select gate layer at the first etch rate includes using an oxidizing agent to oxidize at least a top portion of the substrate underlying the dielectric layer to form an oxide layer. The method further includes etching the select gate layer at a second etch rate lower than the first etch rate to form a second portion of the sidewall of the select gate, wherein the step of etching the select gate layer at the second etch rate includes removing only a top portion of the dielectric layer.
1. A method for forming a semiconductor device, the method comprising:
forming a dielectric layer over a substrate;
forming a select gate layer over the dielectric layer;
etching the select gate layer at a first etch rate to form a first portion of a sidewall of a select gate and to leave remaining portions of the select gate layer covering the dielectric layer, wherein the step of etching the select gate layer at the first etch rate includes using an oxidizing agent to oxidize at least a top portion of the substrate underlying the dielectric layer to form an oxide layer below the dielectric layer, wherein the oxidizing agent is selected from a group consisting of oxygen and helium oxide;
etching the select gate layer at a second etch rate lower than the first etch rate to form a second portion of the sidewall of the select gate, wherein the step of etching the select gate layer at the second etch rate includes removing only a top portion of the dielectric layer, wherein the second etch rate is lower than the first etch rate due to a variation in at least one of an etch power, an etch bias, and an etch chemistry associated with the respective etching step;
removing the oxide layer and any remaining portion of the dielectric layer to expose a portion of the substrate;
forming a charge storage layer overlying exposed portion of the substrate and the sidewall of the select gate;
forming a control gate layer overlying the charge storage layer; and
forming a control gate by patterning the control gate layer and the charge storage layer.
2. The method of claim 1 , wherein the step of forming the charge storage layer comprises forming a layer of one of a group consisting of nanocrystals, nitride, and oxide.
3. The method of claim 1 , wherein the step of etching the select gate layer at the first etch rate comprises using a RF plasma at a first etch power and the step of etching the select gate layer at the second etch rate comprises using the RF plasma at a second etch power lower than the first etch power.
4. The method of claim 1 , wherein the step of etching the select gate layer at the first etch rate comprises using a RF plasma at a first etch bias and the step of etching the select gate layer at the second etch rate comprises using the RF plasma at a second etch bias lower than the first etch bias.
5. The method of claim 1 , wherein the step of etching the select gate layer at the first etch rate comprises using a first etch chemistry and the step of etching the select gate layer at the second etch rate comprises using a second etch chemistry, wherein the second etch chemistry is different from the first etch chemistry.
6. The method of claim 1 further comprising removing the oxide layer and any remaining portion of the dielectric layer to form a recess in the substrate adjacent to the sidewall of the select gate.
7. A method for forming a semiconductor device, the method comprising:
forming a dielectric layer over a substrate;
forming a select gate layer over the dielectric layer;
using a first etch chemistry for etching the select gate layer at a first etch rate to form a sidewall of a select gate and to leave remaining portions of the dielectric layer covering the substrate;
using a second etch chemistry different from the first etch chemistry, selectively etching the dielectric layer;
etching the substrate at a second etch rate lower than the first etch rate to form a recess in the substrate adjacent to the sidewall of the select gate, wherein the step of etching the substrate at the second etch rate includes using an oxidizing agent, wherein the step of etching the substrate at the second etch rate lower than the first etch rate to form the recess in the substrate comprises forming a substantially vertical recess, and wherein the oxidizing agent is selected from a group consisting of oxygen and helium oxide;
forming a charge storage layer overlying any exposed portion of the substrate and the sidewall of the select gate;
forming a control gate layer overlying the charge storage layer; and
forming a control gate by patterning the control gate layer and the charge storage layer.
8. The method of claim 7 , wherein the step of forming the charge storage layer comprises forming a layer of one of a group consisting of nanocrystals, nitride, and oxide.
9. The method of claim 7 , wherein the step of etching the select gate layer at the first etch rate comprises using a RF plasma at a first etch power and the step of etching the substrate at the second etch rate comprises using the RF plasma at a second etch power lower than the first etch power.
10. The method of claim 7 , wherein the step of etching the select gate layer at the first etch rate comprises using a RF plasma at a first etch bias and the step of etching the substrate at the second etch rate comprises using the RF plasma at a second etch bias lower than the first etch bias.
11. The method of claim 7 , wherein the step of etching the substrate at the second etch rate comprises using a third etch chemistry, wherein the third etch chemistry is different from the first etch chemistry.
12. A method for forming a semiconductor device, the method comprising:
forming a dielectric layer over a substrate;
forming a select gate layer over the dielectric layer;
etching the select gate layer at a first etch rate to form a first portion of a sidewall of a select gate and to leave remaining portions of the select gate layer covering the dielectric layer, wherein the step of etching the select gate layer at the first etch rate includes using an oxidizing agent to oxidize at least a top portion of the substrate underlying the dielectric layer to form an oxide layer below the dielectric layer, wherein the oxidizing agent is selected from a group consisting of oxygen and helium oxide;
etching the select gate layer at a second etch rate lower than the first etch rate to form a second portion of the sidewall of the select gate, wherein the step of etching the select gate layer at the second etch rate includes removing only a top portion of the dielectric layer, wherein the second etch rate is lower than the first etch rate due to a variation in at least one of an etch power, an etch bias, and an etch chemistry associated with the respective etching step;
using a wet etch removing the oxide layer and any remaining portion of the dielectric layer to expose a portion of the substrate;
forming a charge storage layer overlying exposed portion of the substrate and the sidewall of the select gate;
forming a control gate layer overlying the charge storage layer; and
forming a control gate by patterning the control gate layer and the charge storage layer.
13. The method of claim 12 , wherein the step of forming the charge storage layer comprises forming a layer of one of a group consisting of nanocrystals, nitride, and oxide.