A comparator is provided. In one embodiment, a method of operating a comparator comprises providing a bias current ( 920 ); comparing an input signal and a reference signal to determine a difference signal and an inverted difference signal ( 930 ); latching the difference signal and the inverted difference signal to generate a first and second latched signals ( 950 ); generating a control signal using at least the first and second latched signals ( 970 ); and controlling the bias current in response to the control signal ( 980 ), wherein the comparing the input signal and the reference signal ( 930 ) is activated and deactivated in response to the controlling the bias current ( 980 ). In another embodiment, a comparator comprises a bias circuit ( 420 ) configured to provide a bias current; a comparator circuit ( 430 ) configured to determine a difference signal and an inverted difference signal by comparing an input signal and a reference signal, wherein the bias current is used to place the comparator circuit ( 430 ) in an active mode; a latch circuit ( 450 ) configured to latch the difference signal and the inverted difference signal to generate a first and second latched signals; a control circuit ( 470 ) configured to generate a control signal using at least the first and second latched signals; and a switch circuit ( 480 ) configured to use the control signal to control the bias current to place the comparator circuit ( 430 ) in an active mode and an inactive mode.
1. A method of operating a comparator, comprising:
providing a bias current;
comparing an input signal and a reference signal to determine a difference signal and an inverted difference signal;
latching said difference signal and said inverted difference signal to generate a first and second latched signals;
generating a control signal using at least said first and second latched signals; and
controlling said bias current in response to said control signal, wherein said comparing an input signal and a reference signal is activated and deactivated in response to said controlling said bias current, wherein said comparing an input signal and a reference signal is activated when said first latched signal is about the same as said second latched signal and is deactivated when said first latched signal is different from said second latched signal.
2. The method of claim 1 , wherein said comparing an input signal and a reference signal is performed by a comparator circuit; and
wherein said bias current is used to place said comparator circuit in an active mode and an inactive mode.
3. The method of claim 1 , wherein said providing a bias current further comprises:
providing a constant current from an output node of a constant current source circuit to an input node of a bias circuit, wherein said bias circuit provides said bias current;
wherein said controlling said bias current in response to said control signal further comprises:
switching a switch in response to said control signal to couple and decouple said output node of said constant current source circuit with said input node of said bias circuit.
4. The method of claim 1 , wherein said providing a bias current further comprises:
mirroring a constant current to provide said bias current;
wherein said controlling said bias current in response to said control signal further comprises:
mirroring said constant current in response to said control signal.
5. The method of claim 4 , wherein said mirroring a constant current to provide said bias current further comprises:
mirroring said constant current received by a first transistor in a second transistor; and
wherein said mirroring said constant current in response to said control signal further comprises:
switching a first switch in response to said control signal to couple and decouple the gate node of said first transistor with the gate node of said second transistor; and
switching a second switch in response to the inverse of said control signal to couple and decouple the gate node of said second transistor with a voltage supply source node.
6. The method of claim 4 , wherein said mirroring a constant current to provide said bias current further comprises:
mirroring said constant current received by a first transistor in a second transistor; and
wherein said mirroring said constant current in response to said control signal further comprises:
switching a switch to couple and decouple the source node of said second transistor with a voltage supply source node.
7. The method of claim 1 , wherein said comparing an input signal and a reference signal is performed by a differential amplifier circuit; and
wherein said bias current is used to place said differential amplifier circuit in an active mode and an inactive mode.
8. The method of claim 1 , wherein said latching said difference signal and said inverted difference signal is performed by a latch circuit, wherein said latch circuit operates in a regenerate state and a reset state; and
wherein said comparing an input signal and a reference signal is activated when at least one of said first latched signal is about the same as said second latched signal and said latch circuit is operated in said regenerate state and
is deactivated when said first latched signal is different from said second latched signal and said latch circuit is operated in said reset state.
9. The method of claim 1 , wherein said comparing an input signal and a reference signal and said latching said difference signal and said inverted difference signal are performed by a latched comparator circuit.
10. A comparator, comprising:
a bias circuit configured to provide a bias current;
a comparator circuit configured to determine a difference signal and an inverted difference signal by comparing an input signal and a reference signal, wherein said bias current is used to place said comparator circuit in an active mode;
a latch circuit configured to latch said difference signal and said inverted difference signal to generate a first and second latched signals;
a control circuit configured to generate a control signal using at least said first and second latched signals; and
a switch circuit configured to use said control signal to control said bias current to place said comparator circuit in an active mode and an inactive mode, wherein said control circuit is further configured to generate said control signal to place said comparator circuit in an active mode when said first latched signal is about the same as said second latched signal and in an inactive mode when said first latched signal is different from said second latched signal.
11. The comparator of claim 10 , wherein said input signal comprises a positive and negative differential input signals;
wherein said reference signal comprises a positive and negative reference signals; and
wherein said comparator circuit further comprises:
a first differential amplifier configured to receive said positive differential input signal and said positive reference signal to determine a first difference signal and an inverted first difference signal;
a second differential amplifier configured to receive said negative differential input signal and said negative reference signal to determine a second difference signal and an inverted second difference signal;
wherein said first difference signal and said inverse second difference signal are combined to form said difference signal; and
wherein said inverted first difference signal and said second difference signal are combined to form said inverted difference signal.
12. The comparator of claim 10 , wherein said latch circuit operates in a regenerate state and a reset state; and
wherein said control circuit is further configured to generate said control signal to place said comparator circuit in an active mode when at least one of said first latched signal is about the same as said second latched signal and said latch circuit is operated in said regenerate state and in an inactive mode when said first latched signal is different from said second latched signal and said latch circuit is operated in said reset state.
13. The comparator of claim 10 , wherein said switch circuit is further configured to couple and decouple the output node of a constant current source with the input node of said bias circuit in response to said control signal, wherein said constant current source is configured to provide a constant current.
14. The comparator of claim 10 , wherein said bias circuit further comprises:
a first transistor configured to receive a constant current;
a second transistor configured to provide a bias current, wherein said first transistor mirrors the constant current in said second transistor; and
wherein said switch circuit further comprises:
a first switch configured to couple and decouple the gate node of said first transistor with the gate node of said second transistor in response to said control signal; and
a second switch configured to couple and decouple the gate node of said second transistor with a voltage supply source node in response to the inverse of said control signal.
15. The comparator of claim 10 , wherein said bias circuit further comprises:
a first transistor configured to receive a constant current;
a second transistor configured to provide a bias current, wherein said first transistor mirrors the constant current in said second transistor; and
wherein said switch circuit further comprises:
a switch configured to couple and decouple the source node of said second transistor with a voltage supply source node in response to said control signal.
16. An analog-to-digital converter, comprising:
a reference circuit configured to generate a reference signal;
a bias circuit configured to provide a bias current;
a comparator circuit configured to compare said reference signal and an input signal to determine a difference signal and an inverted difference signal, wherein said bias current is used to place said comparator circuit in an active mode;
a latch circuit configured to latch said difference signal and said inverted difference signal to generate a first and second latched signals;
a memory circuit configured to store a digital signal using at least one of said first and second latched signals;
an encoder circuit configured to use said digital signal to generate a data sample;
a control circuit configured to generate a control signal, wherein said control circuit uses at least said first and second latched signals; and
a switch circuit configured to use said control signal to control said bias current to place said comparator circuit in an active mode and an inactive mode, wherein said control circuit is further configured to generate said control signal to place said comparator circuit in an active mode when said first latched signal is about the same as said second latched signal and in an inactive mode when said first latched signal is different from said second latched signal.
17. The analog-to-digital converter of claim 16 , wherein said latch circuit operates in a regenerate state and a reset state; and
wherein said control circuit is further configured to generate said control signal to place said comparator circuit in an active mode when at least one of said first latched signal is about the same as said second latched signal and said latch circuit is operated in said regenerate state and in an inactive mode when said first latched signal is different from said second latched signal and said latch circuit is operated in said reset state.