Method and system for integrated circuit power supply management
View Patent ↗A method and system for power supply management in an integrated chip selectively manages the power supplied to the various circuits within the integrated circuit. The integrated circuit includes a combinational logic block, a memory block, a power supply block, and a control block. The power supply block includes multiple power regulators for generating power supply potentials of various magnitudes. The control block receives a power down signal, a clock disable signal, and a temperature threshold signal, and generates control signals for controlling the magnitude of the potential of the power supplied to the combinational logic block and the memory block by the power supply block.
1. In an integrated circuit, a method of power supply management, wherein the integrated circuit comprises a combinational logic block including a plurality of standard cells, and a memory block including a plurality of memory cells, the method comprising:
receiving a power-down signal and activating a low power mode based on the power-down signal;
receiving a clock disable signal that disables one or more clock signals used to operate the integrated circuit;
detecting an operating temperature of the integrated circuit and generating a temperature threshold signal;
providing a source biasing potential to the plurality of memory cells based on the clock disable signal, the power-down signal, and the temperature threshold signal; and
providing a well biasing potential to the plurality of standard cells based on the clock disable signal, the power-down signal, and the temperature threshold signal.
2. The method of power supply management of claim 1 , further comprising providing a trimmed potential to the plurality of standard cells based on the power-down signal and the temperature threshold signal, wherein the trimmed potential is less than a low power mode potential provided to the plurality of standard cells.
3. The method of power supply management of claim 1 , wherein the power-down signal is generated by software.
4. The method of power supply management of claim 3 , wherein the software includes one or more predefined rules including one or more commands for disabling the one or more clock signals received by the integrated circuit.
5. The method of power supply management of claim 4 , wherein the clock disable signal is generated by the software.
6. The method of power supply management of claim 1 , wherein the low power mode includes at least one of a stand-by mode and a stop mode.
7. A system for management of power supplied in an integrated circuit, the integrated circuit comprising a combinational logic block and a memory block, wherein the combinational logic block comprises a plurality of standard cells and the memory block comprises a plurality of memory cells, the system comprising:
a power supply block, connected to the combinational logic block, wherein the power supply block includes,
a first power regulator for providing a first potential, wherein the first power regulator comprises a first amplifier that receives a bandgap reference potential;
a second power regulator for providing a second potential that is less than the first potential, wherein the second power regulator comprises a second amplifier that receives at least one of the bandgap reference potential and a reduced bandgap reference potential;
a third power regulator for providing a well biasing potential to the plurality of standard cells, wherein the third power regulator comprises a third amplifier that receives the bandgap reference potential;
a temperature sensor for detecting an operating temperature of the integrated circuit and generating a temperature threshold signal, wherein the temperature sensor comprises a fourth amplifier that receives the bandgap reference potential and a fourth potential that is proportional to the operating temperature of the integrated circuit, wherein the fourth amplifier generates the temperature threshold signal based on the bandgap reference potential and the fourth potential; and
a control block, connected to the power supply block, and the memory block, wherein the control block includes,
a source bias signal generator that receives a power-down signal, a clock disable signal, and the temperature threshold signal, and generates a source bias signal that is provided to the memory block for switching supply of a source biasing potential to the plurality of memory cells, and wherein based on the power-down signal, a low power mode of the integrated circuit is activated;
a supply selector that receives the power-down signal, the clock disable signal, the temperature threshold signal, the second potential, and the well biasing potential, wherein the supply selector selects at least one of the second potential and the well biasing potential based on the power-down signal, the clock disable signal, and the temperature threshold signal, and provides at least one of the second potential and the well biasing potential to the plurality of standard cells, and
a trim-down signal generator for generating a trim-down signal that activates reduction of the second potential based on the temperature threshold signal and the power-down signal.
8. The power management system of claim 7 , wherein the bandgap reference potential is provided to a positive terminal of the first amplifier, the second amplifier, the third amplifier, and the fourth amplifier.
9. The power management system of claim 7 , wherein the first amplifier, the second amplifier, and the third amplifier are connected in a negative feedback configuration.
10. The power management system of claim 7 , wherein the fourth potential is provided to a negative terminal of the fourth amplifier.
11. The power management system of claim 7 , wherein the clock disable signal disables one or more clock signals received by the integrated circuit, and wherein the clock disable signal is generated external to the integrated circuit.
12. The power management system of claim 7 , wherein the first power regulator is a high power regulator that provides power to the combinational logic block during a high power mode of the integrated circuit, wherein the high power mode is an operational mode of the integrated circuit, and wherein the first potential is a high power regulator potential.
13. The power management system of claim 7 , wherein the second power regulator is a low power regulator that provides power to the memory block during the low power mode of the integrated circuit, and wherein the second potential is a low power regulator potential.
14. The power management system of claim 7 , wherein the third power regulator is a low power regulator that provides power to the memory block during the low power mode of the integrated circuit.
15. The power management system of claim 7 , wherein the power-down signal is generated by software.
16. The power management system of claim 15 , wherein the software includes one or more predefined rules including one or more commands for disabling one or more clock signals received by the integrated circuit.
17. The power management system of claim 15 , wherein the clock disable signal is generated by the software.
18. The power management system of claim 7 , wherein the low power mode includes at least one of a stand-by mode and a stop mode.