Coherency groups of serially coupled processing cores propagating coherency information containing write packet to memory
View Patent ↗A system has a first plurality of cores in a first coherency group. Each core transfers data in packets. The cores are directly coupled serially to form a serial path. The data packets are transferred along the serial path. The serial path is coupled at one end to a packet switch. The packet switch is coupled to a memory. The first plurality of cores and the packet switch are on an integrated circuit. The memory may or may not be on the integrated circuit. In another aspect a second plurality of cores in a second coherency group is coupled to the packet switch. The cores of the first and second pluralities may be reconfigured to form or become part of coherency groups different from the first and second coherency groups.
1. An apparatus comprising:
an integrated circuit including a multi processor core circuit, wherein the multi processor core circuit is operable to include:
a first coherency group, wherein
the first coherency group includes a first plurality of processor cores of the multi processor core circuit,
the processor cores of the first coherency group are serially communicatively coupled to propagate information packets, wherein
each processor core of the first coherency group receives cache coherency information from write packets to a memory generated by other processor cores of the first coherency group;
a second coherency group, wherein
the second coherency group includes a second plurality of processor cores of the multi processor core circuit,
the processor cores of the second coherency group are serially communicatively coupled to propagate information packets, wherein
each processor core of the second coherency group receives cache coherency information from write packets to the memory generated by other processor cores of the second coherency group and does not receive cache coherency information of write packets to the memory generated by the processor cores of the first coherency group;
wherein each processor core of the first coherency group does not receive cache coherency information of write packets to the memory generated by the processor cores of the second coherency group.
2. The apparatus of claim 1 , wherein the integrated circuit further comprises:
a packet switch circuit; and
the memory, the multi processor core circuit communicatively coupled to the memory through the packet switch circuit.
3. The apparatus of claim 1 , wherein the integrated circuit further comprises:
a controller coupled to processor cores of the multi processor core circuit, the controller providing coherency control information for grouping the processor cores of the multi processor core circuit into coherency groups.
4. The apparatus of claim 1 wherein the multi processor core circuit is operable to include:
a third coherency group of processor cores of the multi processor core circuit and a fourth coherency group of processor cores of the multi processor core circuit, wherein
the third coherency group includes at least one processor core of the first plurality of processor cores and at least one processor of the second plurality of processor cores,
the processor cores of the third coherency group are serially communicatively coupled to propagate information packets, wherein
each processor core of the third coherency group receives cache coherency information from write packets to the memory generated by other processor cores of the third coherency group and does not receive cache coherency information of write packets to the memory generated by processor cores of the fourth coherency group, generated by processor cores of the first coherency group not in the third coherency group, and generated by processor cores of the second coherency group not in the third coherency group;
wherein the fourth coherency group includes at least one processor core of the first plurality of processor cores,
the processor cores of the fourth coherency group are serially communicatively coupled to propagate information packets, wherein
each processor core of the fourth coherency group receives cache coherency information from write packets to the memory generated by other processor cores of the fourth coherency group and does not receive cache coherency information of write packets to the memory generated by processor cores of the third coherency group, generated by processor cores of the first coherency group not in the fourth coherency group, and generated by processor cores of the second coherency group not in the fourth coherency group.
5. The apparatus of claim 1 wherein the first coherency group is serially communicatively coupled via communication links between the processor cores of the first coherency group, wherein the communication links includes at least one of the group consisting of optical communication links, wireless radio frequency communication links, and a low voltage differential signaling communication links.