Remote permissions provisioning for storage in a cache and device therefor
View Patent ↗A system and method are disclosed for determining whether to allow or deny an access request based upon one or more descriptors at a local memory protection unit and based upon one or more descriptors a system memory protection unit. When multiple descriptors of a memory protection unit apply to a particular request, the least-restrictive descriptor will be selected. System access information is stored at a cache of a local core in response to a cache line being filled. The cached system access information is merged with local access information, wherein the most-restrictive access is selected.
1. A method comprising:
receiving a first access request to write to a first memory, the first access request including a first address;
determining a first region descriptor at a local memory protection unit includes a first accessibility indicator specifying that writing to locations within a first region including the first address is not permitted;
determining a second region descriptor at the local memory protection unit includes a second accessibility indicator specifying that writing to locations within a second region including the first address is permitted;
determining a first access permission allowing the first access request based on the second accessibility indicator in response to determining the second accessibility indicator is less restrictive than the first accessibility indicator;
determining a third region descriptor at a global memory protection unit includes a third accessibility indicator specifying that writing to locations within a third region including the first address is not permitted; and
determining a second access permission denying the first access request based on the third accessibility indicator; and
denying the first access request at the local memory protection unit based on the second access permission in response to determining the second access permission denying the first access request is more restrictive than the first access permission allowing the request,
wherein the first region descriptor and the second region descriptor are provided at the local memory protection unit included at a first processor core, and the third region descriptor is provided at the global memory protection unit included in a processor system, the global memory protection unit outside the first processor core.
2. The method of claim 1 , wherein the processor system includes a plurality of processor cores including the first processor core.
3. The method of claim 1 , wherein determining the second access permission further comprises determining the second access permission based on a fourth accessibility indicator included at the global memory protection unit, the second access permission determined based on a least-restrictive of the third accessibility indicator and the fourth accessibility indicator.
4. The method of claim 1 , wherein the first access permission is selected from a group consisting of a supervisor-read accessibility indicator, a supervisor-write accessibility indicator, a user-read accessibility indicator, and a user-write accessibility indicator.
5. The method of claim 1 , wherein an accessibility indicator that allows an access of a specific access type is less restrictive than an accessibility indicator that does not allow the access of the specific access type.
6. The method of claim 1 , wherein the first access permission is associated with a range of addresses, the range of addresses including the first address.
7. The method of claim 1 , wherein the first accessibility indicator is associated with a first range of addresses and the second accessibility indicator is associated with a second range of addresses, and the first address being in the first range of addresses and in the second range of addresses.
8. The method of claim 7 , wherein the third accessibility indicator is associated with a third range of addresses, the third range of addresses overlapping one or both of the first range of addresses and the second range of addresses, and the first address being in the third range of addresses.
9. The method of claim 1 , further comprising:
providing an access exception indicator to a processor core associated with the first access request in response to denying the first access request.
10. A method comprising:
determining a first region descriptor at a first memory protection unit at a first processor core includes a first accessibility indicator specifying a request to write to a first address within a first region is not permitted;
determining a second region descriptor at the first memory protection unit includes a second accessibility indicator specifying the request to write to the first address within a second region is permitted;
determining a first access permission allowing the request based on the second accessibility indicator in response to determining the second accessibility indicator is less restrictive than the first accessibility indicator ;
determining a third region descriptor at a second memory protection unit external to the first processor core includes a third accessibility indicator specifying the request to write to the first address within a third region is not permitted;
determining a second access permission denying the request based on the third accessibility indicator; and
denying the request at the first memory protection unit based on the second access permission in response to determining the second access permission denying the request is more restrictive than the first access permission allowing the request.
11. The method of claim 10 , wherein the second access permission information is further determined by both the third accessibility indicator and a fourth accessibility indicator, and further comprising:
determining whether to allow or deny an access request based upon the least-restrictive of the third accessibility indicator and the fourth accessibility indicator.
12. The method of claim 10 , wherein an accessibility indicator that allows an access of a specific access type is less restrictive than an accessibility indicator that does not allow the access of the specific access type.
13. The method of claim 10 , wherein the second memory protection unit is a system memory protection unit that is further coupled to a second processor core that includes a third memory protection unit.
14. A system comprising:
a memory device; and
a processor core including a local memory protection unit, the local memory protection unit to determine first permission information allowing a first access to the memory device in response to determining a first accessibility indicator at a first region descriptor at the local memory protection unit allowing the first access is less restrictive than a second accessibility indicator at a second region descriptor at the local memory protection unit denying the first access; and
a system memory protection unit coupled externally to the processor core, the system memory protection unit to determine second permission information denying the first access based on a third accessibility indicator denying the first access, the local memory protection unit to deny the first access in response to determining the second access permission denying the first access is more restrictive than the first access permission allowing the first access.
15. The system of claim 14 , wherein an accessibility indicator that allows an access of a specific access type is less restrictive than an accessibility indicator that does not allow the access of the specific access type.
16. The system of claim 14 , wherein the system memory protection unit is to provide the second permission information to the processor core.
17. The system of claim 16 , wherein the local memory protection unit is to determine third permission information using the second permission information stored local to the processor core.
18. The system of claim 17 , wherein the local memory protection unit is to determine the third permission information prior to determining whether to allow or deny the first memory access request.