Systems and methods for reconfiguring cache memory
View Patent ↗A microprocessor system is disclosed that includes a first data cache that is shared by a first group of one or more program threads in a multi-thread mode and used by one program thread in a single-thread mode. A second data cache is shared by a second group of one or more program threads in the multi-thread mode and is used as a victim cache for the first data cache in the single-thread mode.
1. A method comprising:
in a computer system executing multiple program threads in multi-thread mode in a processing unit:
accessing a first Level 1 (L1) data cache for a first subset of the threads;
accessing a second L1 data cache for a second subset of the threads;
in the computer system executing a single program thread in single thread mode in the processing unit:
configuring the second L1 data cache as a victim cache for the first L1 data cache upon switching to the single thread mode; and
accessing the first L1 data cache and the victim cache for the single program thread;
in the single thread mode, storing the same information in a first memory management unit (MMU) coupled between a first load/store execution unit and the first L1 data cache, and a second MMU coupled between a second load/store execution unit and the second L1 data cache.
2. The method of claim 1 wherein the first L1 data cache is a write-through cache, the method further comprising:
evicting a cache line from the first L1 cache to the victim cache by fetching a cache line with requested data from a Level 2 (L2) cache to the victim cache.
3. The method of claim 1 wherein the first L1 data cache is a write-through cache, the method further comprising:
moving a cache line from the victim cache to the L1 cache by fetching a cache line with requested data from a L2 cache to the victim cache.
4. The method of claim 1 further comprising:
in response to determining that a cache store miss for requested data occurred in the first L1 data cache:
writing the requested data into only the victim cache.
5. The method of claim 1 further comprising:
in response to determining that a cache store miss for requested data occurred in the first L1 data cache and the victim cache:
writing the requested data into a L2 cache only.
6. The method of claim 1 further comprising:
the victim cache is powered-off to conserve power until a predetermined threshold for cache line eviction is met.
7. The method of claim 1 further comprising:
writing requested data from a L2 cache to the L1 cache;
evicting a cache line from the L1 cache to the victim cache; and
if a dirty cache line is evicted from the victim cache, writing the dirty cache line to the L2 cache.
8. The method of claim 1 further comprising:
upon determining that a cache store miss for requested data occurred in the first L1 data cache, performing at least one of the group consisting of: writing the requested data into the L1 data cache and a L2 cache, writing the requested data into the victim cache and the L2 cache, and writing the requested data to the L2 cache.
9. A processing system comprising:
a first L1 data cache;
a second L1 data cache;
a first load/store execution unit configured to access the first L1 data cache; and
a second load/store execution unit configured to:
access the second L1 data cache in a multi-thread mode, and
in a single thread mode, access the first L1 data cache, wherein the second L1 data cache is configured as a victim cache for the first L1 data cache upon switching to the single-thread mode;
a first memory management unit (MMU) coupled between the first load/store execution unit and the first L1 data cache;
a second MMU coupled between the second load/store execution unit and the second L1 data cache; and
in the single thread mode, the first MMU and the second MMU include the same information.
10. The system of claim 9 further comprising:
in the single-thread mode,
a cache line evicted from the first L1 cache is moved to the victim cache by fetching a cache line with requested data from a Level 2 (L2) cache to the victim cache.
11. The system of claim 9 further comprising:
in the single thread mode,
a cache line is moved from the victim cache to the L1 cache by fetching a cache line with requested data from a L2 cache to the victim cache.
12. The system of claim 9 further comprising:
in the single thread mode, the requested data is written into only the victim cache in response to a cache store miss occurring for requested data in the first L1 data cache.
13. The system of claim 9 further comprising:
in the single thread mode, the requested data is written into a L2 cache only in response to determining that a cache store miss for requested data occurred in the first L1 data cache and the victim cache.
14. The system of claim 9 further comprising:
the victim cache is powered-off to conserve power until a predetermined threshold for cache line eviction is met.
15. The system of claim 9 further comprising:
in the single thread mode,
requested data is written from a L2 cache to the L1 cache;
a cache line is evicted from the L1 cache to the victim cache; and
if a dirty cache line is evicted from the victim cache, the dirty cache line is written into the L2 cache.
16. The system of claim 9 further comprising:
in the single thread mode, at least one of the group consisting of:
the requested data is written into the L1 data cache and a L2 cache,
the requested data is written into the victim cache and the L2 cache, and
the requested data is written into the L2 cache,
is performed for a cache store for the requested data.
17. A microprocessor system comprising:
a first data cache that is shared by a first group of one or more program threads in a multi-thread mode and used by one program thread in a single-thread mode; and
a second data cache that is shared by a second group of one or more program threads in the multi-thread mode and is configured as a victim cache for the first data cache upon switching to the single-thread mode;
a first memory management unit (MMU) coupled between a first load/store execution unit and the first L1 data cache;
a second MMU coupled between a second load/store execution unit and the second L1 data cache; and
in the single thread mode, the first MMU and the second MMU include the same information.
18. The system of claim 17 further comprising:
the first load/store execution unit configured to access the first data cache; and
the second load/store execution unit configured to:
access the second data cache in the multi-thread mode, and
access the first data cache in the single thread mode.
19. The system of claim 17 further comprising:
more than one decoder units;
a first set of execution queues; and
a second set of execution queues;
wherein
during the single-thread mode, the system is configured to allow a single thread to use more than half of the decoder units and the first and second sets of execution queues, and
during the multi-thread mode, the system is configured to allow at least one thread to use half of the decoder units and the first set of execution queues, and at least another thread to use the other half of the decoder units and the second set of execution queues.