Dynamic lockstep cache memory replacement logic
View Patent ↗To facilitate dynamic lockstep support, replacement states and/or logic used to select particular cache lines for replacement with new allocations in accord with replacement algorithms or strategies may be enhanced to provide generally independent replacement contexts for use in respective lockstep and performance modes. In some cases, replacement logic that may be otherwise conventional in its selection of cache lines for new allocations in accord with a first-in, first-out (FIFO), round-robin, random, least recently used (LRU), pseudo LRU, or other replacement algorithm/strategy is at least partially replicated to provide lockstep and performance instances that respectively cover lockstep and performance partitions of a cache. In some cases, a unified instance of replacement logic may be reinitialized with appropriate states at (or coincident with) transitions between performance and lockstep modes of operation.
1. A method of operating a computational system that includes a plurality of processors each having an associated cache partitioned into lockstep and non-lockstep partitions, the method comprising:
dynamically transitioning between a lockstep mode of operation and a non-lockstep mode of operation, wherein in the lockstep mode of operation, the plural processors each execute a same code sequence in temporal correspondence, and wherein in the non-lockstep mode of operation, the plural processors are capable of executing differing code sequences;
maintaining for each of the associated caches both (i) a lockstep version of cache replacement state for use in the lockstep mode relative to its lockstep partition and (ii) a non-lockstep version of cache replacement state for use in the non-lockstep mode relative to its non-lockstep partition; and
in the non-lockstep mode, satisfying one or more non-lockstep mode access requests based on cache hits in the lockstep partition without affecting the lockstep version of cache replacement state.
2. The method of claim 1 , further comprising:
during operation of the computational system, partitioning the associated caches into the lockstep and non-lockstep partitions.
3. The method of claim 1 ,
wherein the maintaining of lockstep and non-lockstep versions of replacement state includes maintaining, with separate respective logic, the respective versions for use in the lockstep and non-lockstep modes.
4. The method of claim 1 ,
wherein the maintaining of lockstep and non-lockstep versions of replacement state includes initializing a least a portion of replacement state in response to a transition between the non-lockstep mode and the lockstep mode.
5. The method of claim 1 , further comprising:
in the non-lockstep mode, freezing the lockstep version of cache replacement state.
6. The method of claim 1 , further comprising:
coincident with transition to the lockstep mode, forcing the lockstep version of cache replacement state to a predetermined value.
7. The method of claim 1 ,
wherein the associated caches are partitioned by cache ways, and
wherein the method further comprises, in the non-lockstep mode, freezing of a lockstep version of local replacement state.
8. The method of claim 7 , further comprising:
in the lockstep mode and responsive to hit in the non-lockstep partition, invalidating the corresponding line in the non-lockstep partition and updating a non-lockstep version of local replacement state in correspondence with the invalidation.
9. The method of claim 7 ,
wherein ways number at least four (4), and
wherein the method further comprises reserving a programmable number of the ways as the lockstep partition.
10. The method of claim 7 ,
wherein the lockstep version of local replacement state and a non-lockstep version of local replacement state include pseudo least recently used (PLRU) states for cache lines represented in the respective non-lockstep and lockstep partitions.
11. The method of claim 1 ,
wherein, in the lockstep mode of operation, the temporal correspondence provides execution, on each of the plural processors, of same respective instructions of the same code sequence in execution cycles that are either identical or exhibit a generally fixed phase relationship.
12. The method of claim 1 ,
wherein the associated caches are partitioned by cache sets.
13. An apparatus comprising:
plural processors dynamically transitionable between lockstep and non-lockstep modes of operation, wherein in the lockstep mode of operation, the plural processors each execute a same code sequence in temporal correspondence, and wherein in the non-lockstep mode of operation, the plural processors are capable of executing differing code sequences;
respective caches coupled to, and associated with, respective ones of the plural processors, the respective caches each partitionable to service lockstep mode access requests solely from a lockstep partition thereof, while allowing non-lockstep mode access requests to be satisfied from either the lockstep partition or a non-lockstep partition of the associated cache; and
each of the respective caches including replacement logic configured to maintain both (i) a lockstep version of replacement state for use in the lockstep mode relative to its lockstep partition and (ii) a non-lockstep version of replacement state for use in the non-lockstep mode relative to its non-lockstep partition, wherein the respective caches satisfy non-lockstep mode access requests based on cache hits in the lockstep partition without affecting the lockstep version of cache replacement state operant upon transition to lockstep mode of operation.
14. The apparatus of claim 13 , further comprising:
a control register that defines the lockstep and non-lockstep partition portions of at least one of the caches.
15. The apparatus of claim 13 , further comprising:
separate, but at least functionally equivalent, instances of the replacement logic configured to maintain the respective lockstep and non-lockstep versions of replacement state for use in the lockstep and non-lockstep modes, respectively.
16. The apparatus of claim 13 , further comprising:
replacement context initialization logic to initialize a least a portion of the lockstep version of replacement state in correspondence with transition from the non-lockstep mode to the lockstep mode.
17. The apparatus of claim 16 , wherein the portion of replacement logic initialized by replacement context initialization logic includes a counter or pointer used to implement a first-in, first-out (FIFO) or pseudo-random replacement algorithm.
18. The apparatus of claim 13 ,
wherein the respective caches are partitionable by cache ways, and
wherein, in the non-lockstep mode, the replacement logic freezes lockstep versions of local replacement state.
19. The apparatus of claim 18 ,
wherein lockstep and non-lockstep versions of the local replacement state each include pseudo least recently used (PLRU) states for cache lines represented in the respective non-lockstep and lockstep partitions.
20. An apparatus comprising:
plural processors dynamically transitionable, without a reboot, between lockstep and non-lockstep modes of operation, wherein in the lockstep mode of operation, the plural processors each execute a same code sequence in temporal correspondence, and wherein in the non-lockstep mode of operation, the plural processors are capable of executing differing code sequences;
respective caches coupled to, and associated with, respective ones of the plural processors, the respective caches each partitionable to service lockstep mode access requests solely from a lockstep partition thereof, while allowing non-lockstep mode access requests to be satisfied from either the lockstep partition or a non-lockstep partition of the associated cache; and
each of the respective caches including replacement logic configured to maintain both (i) a lockstep version of replacement state for use in the lockstep mode relative to its lockstep partition and (ii) a non-lockstep version of replacement state for use in the non-lockstep mode relative to its non-lockstep partition, wherein the respective caches satisfy non-lockstep mode access requests based on cache hits in the lockstep partition without affecting the lockstep version of cache replacement state operant upon transition to lockstep mode of operation,
wherein the respective caches are partitionable by cache ways,
wherein, in the non-lockstep mode, the replacement logic freezes lockstep versions of local replacement state, and
wherein, in the lockstep mode and responsive to a hit in the non-lockstep partition of a particular one of the caches, the particular cache invalidates the corresponding line in the non-lockstep partition.
21. The apparatus of claim 18 ,
wherein ways number at least four (4), and
further comprising a programmable register that specifies a changeable subset of the ways that constitute the lockstep partition.