IP Library › Granted Patent US 8,638,592

Granted Patent B2

US 8,638,592 · App. 13/228,001 · Granted Jan 28, 2014

Dual port static random access memory cell

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Quick Facts

Patent No.: US 8,638,592
App. No.: 13/228,001
Granted: Jan 28, 2014
Kind: B2

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Abstract

An SRAM has at least two sets of pass transistors for coupling at least two sets of bit lines to true and complement data nodes of an SRAM cell based on the assertion of at least two word lines. The cell includes two pull up transistors and two pull down transistors coupled to the true and complement data nodes. None of the pass transistors are implemented in an active area that includes a pull up transistor or a pull down transistor of the cell.

Claims (113)

1. A multi-port SRAM comprising:

a first set of bit lines, the first set of bit lines including a first true bit line and a first complementary bit line;

a second set of bit lines including a second true bit line and a second complementary bit line;

a data node and a complementary data node;

a first set of pass transistors including a first true pass transistor and a first complementary pass transistor, the first true pass transistor for coupling the first true bit line to the data node in response to an assertion of a first word line and the first complementary pass transistor for coupling the first complementary bit line to the complementary data node in response to an assertion of the first word line;

a second set of pass transistors including a second true pass transistor and a second complementary pass transistor, the second true pass transistor for coupling the second true bit line to the data node in response to an assertion of a second word line and the second complementary pass transistor for coupling the second complementary bit line to the complementary data node in response to an assertion of the second word line;

a first pull up transistor including a first current terminal coupled to a first voltage terminal, a second current terminal coupled to the data node, and a control terminal coupled to the complementary data node;

a second pull up transistor including a first current terminal coupled to the first voltage terminal, a second current terminal coupled to the complementary data node, and a control terminal coupled to the data node;

a first pull down transistor including a first current terminal coupled to a second voltage terminal, a second current terminal coupled to the data node, and a control terminal coupled to the complementary data node; and

a second pull down transistor including a first current terminal coupled to the second voltage terminal, a second current terminal coupled to the complementary data node, and a control terminal coupled to the data node;

wherein the first true pass transistor is implemented in an active region that does not include the first pull up transistor, the second pull up transistor, the first pull down transistor, and the second pull down transistor;

wherein the first complementary pass transistor is implemented in an active region that does not include the first pull up transistor, the second pull up transistor, the first pull down transistor, and the second pull down transistor;

wherein the second true pass transistor is implemented in an active region that does not include the first pull up transistor, the second pull up transistor, the first pull down transistor, and the second pull down transistor;

wherein the second complementary pass transistor is implemented in an active region that does not include the first pull up transistor, the second pull up transistor, the first pull down transistor, and the second pull down transistor; and

wherein the second true pass transistor is located in a first active region, the first pull down transistor is located in a second active region, and first pull up transistor is located in a third active region, wherein the second active region is located between the first active region and the third active region on a substrate.

2. The multi-port SRAM of claim 1 wherein the first true pass transistor is located in the same active region as the second true pass transistor and the first complementary pass transistor is located in the same active region as the second complementary pass transistor.

3. The multi-port SRAM of claim 2 wherein the first true pass transistor and the second true pass transistor are located in a first active region and the first complementary pass transistor and the second complementary pass transistor are located in a second active region.

4. The multi-port SRAM of claim 3 wherein the first pull up transistor, the second pull up transistor, the first pull down transistor and the second pull down transistor are located in active regions of a substrate between the first active region and the second active region.

5. The multi-port SRAM of claim 1 wherein the first true pass transistor is located in a different active region than the first complementary pass transistor and wherein the second true pass transistor is located in a different active region than the second complementary pass transistor.

6. The multi-port SRAM of claim 1 wherein the second complementary pass transistor is located in a fourth active region, the second pull down transistor is located in a fifth active region, and second pull up transistor is located in a sixth active region, wherein the fifth active region is located between the fourth active region, and the sixth active region on the substrate.

7. The multi-port SRAM of claim 6 wherein the first and fourth active regions occupy the same amount of substrate area, the second and fifth active regions occupy the same amount of substrate area, and the third and sixth active regions occupy the same amount of substrate area.

8. A multi-port SRAM comprising:

a first set of bit lines, the first set of bit lines including a first true bit line and a first complementary bit line;

a second set of bit lines including a second true bit line and a second complementary bit line;

a data node and a complementary data node;

a first interconnect located over a substrate, the first interconnect coupling a current terminal of the first true pass transistor and a current terminal of the second true pass transistor to the second current terminal of the first pull down transistor and the second current terminal of the first pull up transistor; and

a second interconnect located over a substrate, the second interconnect coupling a current terminal of the first complementary pass transistor and a current terminal of the second complementary pass transistor to the second current terminal of the second pull down transistor and the second current terminal of the second pull up transistor;

9. The multi-port SRAM of claim 8 wherein the first interconnect has the same size and shape as the second interconnect.

10. A multi-port SRAM comprising:

a first set of bit lines, the first set of bit lines including a first true bit line and a first complementary bit line;

a second set of bit lines including a second true bit line and a second complementary bit line;

a data node and a complementary data node;

wherein the first pull down transistor is implemented in an active region that does not include the first pull up transistor, the second pull up transistor, the first true pass transistor, the second true pass transistor, the second pull down transistor, the first complementary pass transistor, and the second complementary pass transistor.

11. A multi-port SRAM comprising:

a first set of bit lines, the first set of bit lines including a first true bit line and a first complementary bit line;

a second set of bit lines including a second true bit line and a second complementary bit line;

a data node and a complementary data node;

wherein:

the first pull up transistor, the second pull up transistor, the first true pass transistor, the second true pass transistor, the first pull down transistor, the second pull down transistor, the first complementary pass transistors, and the second complementary pass transistor are of a first cell of the multi-port SRAM, wherein the SRAM includes a plurality of cells arranged in columns wherein the plurality of cells have the same circuit configuration as the first cell;

the first cell is located in a first column of cells of the plurality of columns;

the first true pass transistor and the second true pass transistor of each cell of the first column is located in a first active region; and

the first complementary pass transistor and the second complementary pass transistor of each cell of the first column is located in a second active region.

12. The multi-port SRAM of claim 11 wherein:

the first pull down transistor of the first cell is located in a third active region, wherein only one other pull down transistor of a cell of the first column is located in the third active region; and

the second pull down transistor of the first cell is located in a fourth active region, wherein only one other pull down transistor of a cell of the first column is located in the fourth active region.

13. The multi-port SRAM of claim 11 wherein:

the first pull up transistor of the first cell is located in a third active region, wherein only one other pull up transistor of a cell of the first column is located in the third active region; and

the second pull up transistor of the first cell is located in a fourth active region, wherein only one other pull up transistor of a cell of the first column is located in the fourth active region.

14. A multi-port SRAM comprising:

a first set of bit lines, the first set of bit lines including a first true bit line and a first complementary bit line;

a second set of bit lines including a second true bit line and a second complementary bit line;

a data node and a complementary data node;

wherein:

the first true pass transistor, the second true pass transistor, the first complementary pass transistor and the second complementary pass transistor are implemented in active regions that within a boundary of the first cell have a rectangular shape.

15. The multi-port SRAM of claim 14 wherein the first true pass transistor and the second true pass transistor are located in a first active region and the first complementary pass transistor and the second complementary pass transistor are located in a second active region.

16. A multi-port SRAM comprising:

a first set of bit lines, the first set of bit lines including a first true bit line and a first complementary bit line;

a second set of bit lines including a second true bit line and a second complementary bit line;

a data node and a complementary data node;

wherein:

the first true pass transistor is located in a first active region and the first complementary pass transistor is located in a second active region, wherein within a boundary of the first cell, the first active region and the second active region have the same size and shape.

Assignments (22)

CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020

From: MORGAN STANLEY SENIOR FUNDING, INC.

To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.

Reel/Frame 052917/0001 →

CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020

From: MORGAN STANLEY SENIOR FUNDING, INC.

To: NXP B.V.

Reel/Frame 052915/0001 →

CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019

From: CITIBANK, N.A.

To: MORGAN STANLEY SENIOR FUNDING, INC.

Reel/Frame 053547/0421 →

RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019

From: MORGAN STANLEY SENIOR FUNDING, INC.

To: NXP B.V.

Reel/Frame 050744/0097 →

CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019

From: MORGAN STANLEY SENIOR FUNDING, INC.

To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.

Reel/Frame 048734/0001 →

CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017

From: FREESCALE SEMICONDUCTOR INC.

To: NXP USA, INC.

Reel/Frame 044209/0047 →

CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017

From: CITIBANK, N.A.

To: MORGAN STANLEY SENIOR FUNDING, INC.

Reel/Frame 041703/0536 →

CHANGE OF NAME Recorded Nov 8, 2016

From: FREESCALE SEMICONDUCTOR, INC.

To: NXP USA, INC.

Reel/Frame 040632/0001 →

RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016

From: MORGAN STANLEY SENIOR FUNDING, INC.

To: NXP B.V.

Reel/Frame 040928/0001 →

RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016