Systems and methods for data conversion
View Patent ↗Systems and methods are provided for converting analog data to digital data that can include performing N successive analog subtractions from an initial data charge Qin. The analog subtractions are performed using an amplifier coupled to a discharge capacitor and a divider circuit coupled to an input of the amplifier. The divider circuit includes a first capacitor, a second capacitor, and a switch to alternately divide a remaining charge Q by 2 N between the first and second capacitors until the remaining charge Qin at the amplifier is below a threshold value. A compensating circuit compensates for fluctuations in the charge held by the first and second capacitors due to operation of the switch.
1. A computer processing system comprising:
an analog to digital converter ADC circuit that includes:
a discharge circuit including:
an amplifier and
a discharge capacitor coupled to the amplifier;
a divider circuit coupled to the discharge circuit, the divider circuit including:
a first divider capacitor,
a first divider switch coupled in parallel to the first divider capacitor,
a second divider capacitor coupled in parallel to the first divider capacitor and the first divider switch,
a third divider switch coupled in series between the first divider capacitor and the second divider capacitor; and
a charge injection compensation circuit coupled to the discharge circuit and the divider circuit;
a comparator including a first input coupled to an output of the amplifier,
wherein the charge injection compensation circuit includes a data switch coupled in series between the output of the amplifier and the first input to the comparator.
2. The computer processing system of claim 1 wherein the charge injection compensation circuit includes:
a voltage source coupled in parallel to the first divider capacitor.
3. The computer processing system of claim 1 wherein the charge injection compensation circuit includes:
an input switch coupled in parallel between the first divider capacitor and the first divider switch.
4. The computer processing system of claim 2 wherein the charge injection compensation circuit includes:
a copy switch coupled in series with the voltage source.
5. The computer processing system of claim 1 wherein
the first divider switch is coupled between the first ground level and the third divider switch, and the first and second divider capacitors are coupled between a second ground level and the third divider switch, and
a first input of the amplifier is coupled to a first ground level.
6. The computer processing system of claim 1 wherein
the divider circuit is coupled to the discharge circuit via a first ground level, and
the discharge capacitor is coupled between an output of the amplifier and the first ground level.
7. The computer processing system of claim 1 further comprising:
a second divider switch coupled in parallel to the second divider capacitor, wherein the second divider switch is coupled between a first ground level and the third divider switch;
a comparator including a first comparator input and a second comparator input, wherein the first comparator input is coupled to the output of the amplifier and the second comparator input is coupled to an output of the divider circuit.
8. The computer processing system of claim 7 further comprising:
a fourth switch coupled to the second comparator input, the fourth switch including one terminal coupled between the first divider capacitor and the third divider switch, and a second terminal coupled between the second divider capacitor and the third divider switch.
9. The computer processing system of claim 1 wherein the first and second divider capacitors generate successive Q/2 N charges that are removed from the discharge capacitor through the amplifier.
10. A method for converting an analog signal to a digital signal in a processing system comprising:
performing N successive analog subtractions from an initial data charge Qin, wherein the analog subtractions are performed using an amplifier coupled to a discharge capacitor and a divider circuit coupled to an input of the amplifier, and the divider circuit includes a first capacitor, a second capacitor, and a switch to alternately divide a remaining charge Q by 2 N between the first and second capacitors until the remaining charge Qin at the amplifier is below a threshold value; and
compensating for fluctuations in the charge held by the first and second capacitors due to operation of the switch by operating a data switch to connect a comparator to an output of the amplifier.
11. The method of claim 10 wherein the compensating for fluctuations includes operating an input switch to open a connection to the first capacitor.
12. The method of claim 10 further the compensating for fluctuations further includes operating a copy switch and a voltage source coupled in parallel to the first capacitor.
13. The method of claim 10 wherein:
a p-input switch is coupled between the first divider capacitor and the first divider switch,
a m-input switch is coupled between the second divider capacitor and the second divider switch,
a copy switch is coupled in series with the voltage source;
a comparator including a first input is coupled to an output of the amplifier, and
a data switch is coupled in series between the output of the amplifier and the first input to the comparator.
14. A semiconductor device comprising:
a discharge capacitor;
an amplifier coupled to the discharge capacitor;
a divider circuit coupled to the amplifier and the discharge capacitor; and
a compensation circuit coupled to the divider circuit and the amplifier that includes
a p-input switch coupled between a p-input to a comparator and the divider circuit,
a m-input switch coupled between a m-input to the comparator and the divider circuit,
a copy switch coupled in series with the voltage source between p-input switch and data switch, and
a data switch coupled in series between an output of amplifier and the p-input to comparator.
15. The semiconductor device of claim 14 , the divider circuit further comprising:
a third divider switch; and
first and second divider capacitors,
wherein the first divider switch is coupled between a first ground level and the third divider switch, and the first and second divider capacitors, are coupled between a second ground level and the third divider switch,
a first input of the amplifier is coupled to a first ground level,
the divider circuit is coupled to the discharge capacitor via a first ground level,
the discharge capacitor is coupled between an output of the amplifier and the first ground level.
16. The semiconductor device of claim 14 further comprising:
a comparator including a first comparator input and a second comparator input, wherein the first comparator input is coupled to the output of the amplifier and the second comparator input is coupled to an output of the divider circuit; and
the divider circuit further comprises:
a third divider switch;
first and second divider capacitors;
a second divider switch coupled in parallel to the second divider capacitor, wherein the second divider switch is coupled between a first ground level and the third divider switch; and
a fourth switch coupled to the second comparator input, the fourth switch including one terminal coupled between the first divider capacitor and the third divider switch, and a second terminal coupled between the second divider capacitor and the third divider switch.
17. The semiconductor device of claim 14 wherein the divider circuit generates successive Q/2 N charges that are removed from the discharge capacitor through the amplifier.
18. The semiconductor device of claim 14 further comprising:
a comparator coupled to the amplifier and the divider circuit, wherein the divider circuit includes a first capacitor, a second capacitor, and a switch that is operated to alternately divide a remaining charge Q by 2 N using the first and second capacitors until the charge Qin at the amplifier is below a threshold value in the process of converting analog data to digital data.